Semiconductor device

Patent metadata

Field	Value
Publication number	US-10056493-B2
Application number	US-201715853875-A
Country	US
Kind code	B2
Filing date	Dec 25, 2017
Priority date	May 20, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
an oxide-semiconductor layer on a first gate electrode on said substrate;
two source/drain regions on said oxide-semiconductor layer;
a first dielectric layer covering on said oxide-semiconductor layer and said two source/drain regions;
a second gate between said two source/drain regions and partially covering said oxide-semiconductor layer; and
a charge storage structure between said first gate electrode and said oxide-semiconductor layer, wherein said first dielectric layer covers the sidewall of said charge storage structure.

2. The semiconductor device of claim 1 , wherein said first dielectric layer comprises a multilayer structure, and the lower surface of said multilayer structure further covers the sidewall of said charge storage structure, and the upper surface of said multilayer structure is flush with said second gate electrode.

3. The semiconductor device of claim 1 , wherein a material of said first dielectric layer comprises rare earth oxide or oxide-semiconductor.

4. The semiconductor device of claim 1 , wherein said charge storage structure comprises an oxide-nitride-oxide structure.

5. The semiconductor device of claim 1 , wherein said charge storage structure comprises a floating gate.

6. The semiconductor device of claim 5 , further comprising:
a second dielectric layer covering on said floating gate; and
a third dielectric layer between said first gate electrode and said floating gate.

7. The semiconductor device of claim 1 , wherein said charge storage structure completely covers said first gate electrode in a projection direction.

8. The semiconductor device of claim 1 , wherein said charge storage structure partially covers said first gate electrode in a projection direction.

9. The semiconductor device of claim 1 , wherein said charge storage structure overlaps said two source/drain regions in a projection direction.

Assignees

• United Microelectronics Corp

Inventors

• Zhou Zhibiao
• Chen Ding-Lung
• Lin Chen-Bin
• Wang Sanpo
• Lee Chung-Yuan
• Ku Chi-Fa

Classifications

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H01L29/788

  Electricity · mapped topic

• H01L29/78609 Primary

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic

• H01L29/78648

  Electricity · mapped topic