Semiconductor device

US10056450B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10056450-B2
Application numberUS-201515123404-A
CountryUS
Kind codeB2
Filing dateJan 29, 2015
Priority dateMar 25, 2014
Publication dateAug 21, 2018
Grant dateAug 21, 2018

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a semiconductor substrate with: a drift layer; a base layer; and a collector layer and a cathode layer. In the semiconductor substrate, when a region operating as an IGBT device is an IGBT region and a region operating as a diode device is a diode region, the IGBT and diode regions are arranged alternately in a repetitive manner; a damaged region is arranged on a surface portion of the diode region in the semiconductor substrate. The IGBT and diode regions are demarcated by a boundary between the collector and cathode layers; and a surface portion of the IGBT region includes: a portion having the damaged region at a boundary side with the diode region; and another portion without the damaged region arranged closer to an inner periphery side relative to the boundary side.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising: a semiconductor substrate including: a drift layer having a first conductivity type; a base layer having a second conductivity type that is arranged at a surface portion of the drift layer; and a collector layer having the second conductivity type and a cathode layer having the first conductivity type that are arranged at a side of the drift layer opposite to another side of the drift layer facing the base layer, wherein: when a region operating as an IGBT device in the semiconductor substrate is an IGBT region and a region operating as a diode device in the semiconductor substrate is a diode region, the IGBT region and the diode region are arranged alternately in a repetitive manner; a damaged region is arranged at a surface portion of the diode region in the semiconductor substrate; the IGBT region and the diode region are demarcated by a boundary between the collector layer and the cathode layer; a surface portion of the IGBT region includes: a portion that has the damaged region, which has a length along a surface direction of the semiconductor substrate equal to or larger than the thickness of the semiconductor substrate, at a boundary side with the diode region; and another portion not having the damaged region that is arranged closer to an inner periphery side relative to the boundary side; and a width of a region where the damaged region is not arranged equals one half or more of a width of the entire IGBT region. 2. The semiconductor device according to claim 1 , wherein: the semiconductor substrate includes a periphery region surrounding the IGBT region and the diode region; and the periphery region includes the collector layer having the second conductivity type arranged adjacent to the cathode layer and is demarcated from the diode region by the boundary between the collector layer and the cathode layer, and includes the damaged region, which has a length along the surface direction of the semiconductor substrate twice or more larger than the thickness of the semiconductor substrate, at a part of a surface portion on the boundary side with the diode region. 3. The semiconductor device according to claim 1 , wherein the damaged region arranged at the IGBT region has an area, which is arranged on both end sides of the boundary between the diode region and the IGBT region, with a length along the surface direction of the semiconductor substrate longer than an area of the damaged region arranged at a central portion between both ends of the boundary. 4. The semiconductor device according to claim 1 , wherein: in the IGBT region, one portion of the base layer is a channel region and a remaining portion of the base layer is a float region; in the IGBT region, an emitter region having the first conductivity type is arranged at a surface portion of the channel region; in the IGBT region, a hole stopper layer having the first conductivity type is arranged in the float region and splits the float region in a thickness direction of the semiconductor substrate; and, in the IGBT region, a carrier storage layer having the first conductivity type with a higher impurity concentration than the drift layer is arranged between the channel region and the drift layer. 5. The semiconductor device according to claim 1 , wherein: the entire IGBT region extends in a lateral direction parallel to an extension direction of the collector layer across the semiconductor substrate above the collector layer.

Assignees

Inventors

Classifications

  • being group IV material · CPC title

  • Diffusion lifetime killers · CPC title

  • Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

  • Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US10056450B2 cover?
A semiconductor device includes a semiconductor substrate with: a drift layer; a base layer; and a collector layer and a cathode layer. In the semiconductor substrate, when a region operating as an IGBT device is an IGBT region and a region operating as a diode device is a diode region, the IGBT and diode regions are arranged alternately in a repetitive manner; a damaged region is arranged on a…
Who is the assignee on this patent?
Denso Corp
What technology area does this patent fall under?
Primary CPC classification H01L29/063. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 21 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).