Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10056407-B2
Application number	US-201615061621-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Mar 4, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A semiconductor device includes a first gate structure disposed on a substrate. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode and first sidewall spacers disposed on both side faces of the first gate electrode and the first cap insulating layer. The semiconductor device further includes a first protective layer formed over the first cap insulating layer and at least one of the first sidewall spacers. The first protective layer includes at least one selected from the group consisting of AlON, AlN and amorphous silicon.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a first gate structure and a second gate structure over a substrate, the first gate structure including a first gate electrode, a first cap insulating layer disposed over the first gate electrode and first sidewall spacers disposed on both side faces of the first gate electrode and the first cap insulating layer, the second gate structure including a second gate electrode, a second cap insulating layer disposed over the second gate electrode and second sidewall spacers disposed on both side faces of the second gate electrode and the second cap insulating layer;
forming a first source/drain region in an area between the first gate structure and the second gate structure;
forming a first insulating layer over the first source/drain region and between the first gate structure and the second gate structure;
after the first insulating layer is formed, forming a first space over the first cap insulating layer and over the first sidewall spacers by recessing the first cap insulating layer and the first sidewall spacers, and a second space over the second cap insulating layer and over the second sidewall spacers by recessing the second cap insulating layer and the second sidewall spacers; and
forming a first protective layer in the first space and a second protective layer in the second space;
after the first and second protective layers are formed, removing the first insulating layer, to expose the first source/drain region;
after the first insulating layer is removed, forming a second insulating layer to cover the first and second gate structures having the first and second protective layers;
removing a part of the second insulating layer above the source/drain region to form a contact hole; and
filling the contact hole with a conductive material to form a contact plug that is in contact with the source/drain region,
wherein the first and second protective layers include at least one selected from the group consisting of a metal nitride based material and amorphous silicon.

2. The method of claim 1 , wherein the metal nitride based material is AlON or AlN.

3. The method of claim 1 , wherein the amorphous silicon is boron-doped amorphous silicon.

4. The method of claim 1 , wherein a material of the first and second sidewall spacers, a material of the first and second cap insulating layer, and a material of the first insulating layer are different from each other.

5. The method of claim 1 , wherein:
the first and second sidewall spacers are made of SiOCN,
the first and second cap insulating layers are made of SiN, and
the first insulating layer is made of SiO 2 .

6. The method of claim 1 , wherein:
the recessing the first and second cap insulating layers is performed by selectively etching the first and second cap insulating layers against the first and second sidewall spacers, and
after the first and second cap insulating layers are recessed, the recessing the first and second sidewall spacers is performed by selectively etching the first and second sidewall spacers against the first and second cap insulating layers.

7. The method of claim 1 , wherein:
after the forming the first insulating layer, the recessing the first and second sidewall spacers is performed by selectively etching the first and second sidewall spacers against the first and second cap insulating layers, and after the forming the first insulating layer and before
after the first and second sidewall spacers are recessed, the recessing the first and second cap insulating layers is performed by selectively etching the first and second cap insulating layers against the first and second sidewall spacers.

8. The method of claim 1 , wherein when forming the contact hole, corner parts of the first and second protective layers and corner parts of the first and second sidewall spacers located under the first and second protective layers, respectively, are etched but the first and second cap insulating layers are not etched.

9. A method of manufacturing a semiconductor device, the method comprising:
forming a first gate structure and a second gate structure over a substrate, the first gate structure including a first gate electrode, a first cap insulating layer disposed over the first gate electrode and first sidewall spacers disposed on both side faces of the first gate electrode and the first cap insulating layer, the second gate structure including a second gate electrode, a second cap insulating layer disposed over the second gate electrode and second sidewall spacers disposed on both side faces of the second gate electrode and the second cap insulating layer;
forming a first source/drain region in an area between the first gate structure and the second gate structure;
forming a first insulating layer over the first source/drain region and between the first gate structure and the second gate structure;
after the forming the first insulating layer, recessing the first and second cap insulating layers;
recessing the first and second sidewall spacers to form a first space over the first cap insulating layer that is recessed and the first sidewall spacers that are recessed and a second space over the second cap insulating layer that is recessed and the second sidewall spacers that are recessed;
forming a first protective layer in the first space and a second protective layer in the second space;
forming a second insulating layer over the first and second gate structures having the first and second protective layers;
forming a contact hole over the source/drain region so as to expose the source/drain region; and
filling the contact hole with a conductive material to form a contact plug that is in contact with the source/drain region,
wherein when forming the contact hole, corner parts of the first and second protective layers and corner parts of the first and second sidewall spacers located under the first and second protective layers, respectively, are etched but the first and second cap insulating layers are not etched.

10. The method of claim 9 , wherein the first and second protective layers include at least one selected from the group consisting of a metal nitride based material and amorphous silicon.

11. The method of claim 10 , wherein the metal nitride based material is AlON or AlN.

12. The method of claim 9 , wherein the amorphous silicon is boron-doped amorphous silicon.

13. The method of claim 9 , wherein a material of the first and second sidewall spacers, a material of the first and second cap insulating layer, and a material of the first insulating layer are different from each other.

14. The method of claim 9 , wherein:
the first and second sidewall spacers are made of SiOCN,
the first and second cap insulating layer is made of SiN, and
the first insulating layer is made of SiO 2 .

15. The method of claim 9 , wherein the recessing the first and second cap insulating layers is performed before the recessing the first and second sidewall spacers.

16. The method of claim 9 , wherein the recessing the first and second sidewall spacers is performed after the forming the first insulating layer and before the recessing the first and second cap insulating layers is performed.

17. The method of claim 9 , wherein an upper surface of the first and second cap insulating layers that are recessed is located substantially at a same level as an upper surface of the first and second sidewall spacers that are recessed.

18. A method of manufacturing a semiconductor device, t

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shen Hsiang-Ku
• Huang Yu-Lien
• Huang Wilson
• Chen Janet
• Yeh Jeng-Ya David

Classifications

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L21/76897

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic