Multilayer ceramic capacitor
US-2017365412-A1 · Dec 21, 2017 · US
US10056192B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10056192-B2 |
| Application number | US-201715457171-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 13, 2017 |
| Priority date | Jun 20, 2016 |
| Publication date | Aug 21, 2018 |
| Grant date | Aug 21, 2018 |
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A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode containing a base metal and coupled to one of the external electrodes; a dielectric layer stacked on the first internal electrode and containing a ceramic material and the base metal; and a second internal electrode stacked on the dielectric layer, containing the base metal, and coupled to another one of the external electrodes, wherein a concentration of the base metal in each of five regions, which are equally divided regions of a region between locations 50 nm away from the first and second internal electrodes in a stacking direction between the first and second internal electrodes, is within ±20% of an average of the concentrations of the base metal in the five regions, and the dielectric layer has a thickness of 0.6 μm or less.
Opening claim text (preview).
What is claimed is: 1. A multilayer ceramic capacitor comprising: a pair of external electrodes; a first internal electrode that contains nickel and is coupled to one of the pair of external electrodes; a dielectric layer that is stacked on the first internal electrode and contains a ceramic material and nickel, the ceramic material including barium and titanium; and a second internal electrode that is stacked on the dielectric layer, contains nickel, and is coupled to another one of the pair of external electrodes, wherein a concentration of nickel in each of five regions is within ±20% of an average of the concentrations of nickel in the five regions, the concentration of nickel being an atomic concentration ratio of nickel to barium and titanium, the five regions being obtained by dividing a region of the dielectric layer equally into five in a stacking direction, the region of the dielectric layer being located from a location 50 nm away from the first internal electrode to a location 50 nm away from the second internal electrode in the stacking direction between the first internal electrode and the second internal electrode, the dielectric layer has a thickness of 0.6 μm or less, and the region located from the location 50 nm away from the first internal electrode to the location 50 nm away from the second internal electrode includes both a crystal grain of the ceramic material and a crystal grain boundary of the crystal grain. 2. The multilayer ceramic capacitor according to claim 1 , wherein the concentration of nickel in each of the five regions is within ±10% of the average of the concentrations of nickel in the five regions. 3. The multilayer ceramic capacitor according to claim 1 , wherein the concentration of nickel in each of the five regions is within ±5% of the average of the concentrations of nickel in the five regions. 4. The multilayer ceramic capacitor according to claim 1 , wherein an average grain size in the dielectric layer is 200 nm or less. 5. The multilayer ceramic capacitor according to claim 1 , wherein the ceramic material is BaTiO 3 . 6. The multilayer ceramic capacitor according to claim 1 , wherein a plurality of dielectric layers are stacked across an internal electrode, and 80% or more of the plurality of dielectric layers are the dielectric layer. 7. The multilayer ceramic capacitor according to claim 1 , wherein a number of dielectric layers stacked in the multilayer ceramic capacitor is 200 or greater. 8. The multilayer ceramic capacitor according to claim 1 , wherein the concentration of nickel is measured by TEM (Transmission Electron Microscope).
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