Apparatuses and methods for flexible fuse transmission

Patent metadata

Field	Value
Publication number	US-10056154-B2
Application number	US-201715668586-A
Country	US
Kind code	B2
Filing date	Aug 3, 2017
Priority date	Sep 14, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

First claim

What is claimed is:

1. An apparatus comprising:
a data bus; and
a first circuit block coupled to the data bus, wherein the first circuit block comprises:
a plurality of latch circuits, each of the plurality of latch circuits being coupled to the data bus and configured, when activated, to latch information on the data bus;
a pointer circuit configured to activate a different one of the plurality of latch circuits each time the pointer circuit receive a load clock pulse;
a circuit node supplied with a control signal, the control signal is configured to be at an active level when the first circuit block is selected and at an inactive level when the first circuit block is not selected; and
a gate circuit coupled to receive the load clock pulse and the control signal, the gate circuit being configured to be allowed to supply the load clock pulse to the pointer circuit responsive to the control signal being at the active level and prevented from supplying the load clock pulse to the pointer circuit responsive to the control signal being at the inactive level.

2. The apparatus of claim 1 , further comprising:
a second circuit block configured to provide a string of first data to the data bus, the second circuit block being further configured to provide a string of second data in association respectively with the string of first data, at least one of the string of second data having a first state, and remaining one or ones of the string of second data having a different state from the first state; and
a decoder circuit configured to decode each of the string of second data, the decoder circuit being further configured to set the control signal at the active level responsive to the at least one of the string of second data having the first state and at the inactive level responsive to the remaining one or ones of the string of second data having the different state.

3. The apparatus of claim 2 , wherein the second circuit block comprises a fuse array circuit, the fuse array circuit comprising a plurality of fuse arrays, each of the plurality of fuse arrays being configured to store in pair defective address information as the first data and bank select information as the second data, the fuse array circuit being configured to access each of the plurality of fuse arrays to provide the defective address information and the bank select information in pair.

4. The apparatus of claim 3 , wherein the plurality of fuse arrays includes a first fuse array and a second fuse array, the first fuse array being configured to store first defective address information and first bank select information, the second fuse array being configured to store second defective address information and second bank select information, and the first bank select information having the first state and the second bank select information having the different state so that the first defective address information is latched in a first latch circuit of the plurality of latch circuits of the first circuit block and the second defective address information is not latched any one of the plurality of latch circuits of the first circuit block.

5. The apparatus of claim 4 , wherein the plurality of fuse arrays further includes a third fuse array, the third fuse array being configured to store third defective address information and first bank select information so that the third defective address information is latched in a second latch circuit of the plurality of latch circuits of the first circuit block.

6. The apparatus of claim 1 ,
wherein the first circuit block further comprises a plurality of flag latches provided correspondingly to the plurality of latch circuits, each of the flag latches being configured to store one of first flag information and second flag information, the first flag information indicating that an associated latch circuit is valid, and the second flag information indicating that the associated latch circuit is invalid;
wherein the pointer circuit is further configured to be disabled from activating one or ones of the plurality of latch circuits indicated as being invalid by the second flag information stored in corresponding one or ones of the plurality of flag latches, irrespective of the pointer circuit receiving the load clock pulse.

7. The apparatus of claim 6 , wherein each of the plurality of flag latches is coupled to the data bus and configured, when activated, to store one of the first flag information and the second flag information through the data bus.

8. The apparatus of claim 7 , wherein the pointer circuit is further configured to activate each of the plurality of flag latches prior to activating any one of the plurality of latch circuits.

9. The apparatus of claim 1 ,
wherein the apparatus further comprises a second circuit block configured to provide a first data to the data bus, the second circuit block being further configured to provide a string of second data to the data bus after providing the first data, and the first data having one of a first state and a different state from the first state, and
wherein the first circuit block further comprises a decoder circuit configured to decode the first data, the decoder circuit being further configured to set the control signal at the active level responsive to the first data having the first state and at the inactive level responsive to the first data having the different state.

10. The apparatus of claim 9 , wherein the decoder circuit is further configured, responsive to the first data having the first state, to keep the control signal at the active level at least until each of the string of second data is latched in an associated one of the plurality of latch circuits of the first circuit block.

11. The apparatus of claim 10 , wherein the second circuit block comprises a fuse array circuit, the fuse array circuit comprising a first fuse array and a plurality of second fuse arrays, the first fuse array being configured to store bank select information, each of the second fuse arrays being configured to store defective address information, and the fuse array circuit being configured to access the first fuse array and then further access each of the plurality of second fuse arrays to provide the data bus with the first data as the bank select information and with the string of second data each as the defective address information.

12. The apparatus of claim 11 , wherein the bank select information stored in the first fuse array has the first state so that the defective address information stored in each of the plurality of second fuse arrays is latched in an associated one of the plurality of latch circuits of the first circuit block.

13. The apparatus of claim 12 , wherein each of the plurality of latch circuits is further coupled to the circuit node so that the defective address information stored in each of the plurality of second fuse arrays is latched in an associated one of the plurality of latch circuits of the first circuit block together with the active level of the control signal.

14. The apparatus of claim 11 , wherein the bank select information stored in the first fuse array has the different state so that the defective address information stored in any one of the plurality of second fuse arrays is prevented from being latched in any one of the plurality of latch circuits of the first circuit block.

15. An apparatus comprising:
a fuse data bus;
a fuse block configured to provide a first string of defective address information to the fuse data bus;
a first redundant circuit block coupled to the fuse data bus; and
a second redundant circuit block coupled to th

Assignees

• Micron Technology Inc

Inventors

• Fujiwara Yoshinori
• Yoshida Kenji
• Someya Minoru
• Noda Hiromasa

Classifications

• G11C29/785 Primary

  with redundancy programming schemes · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C29/76 Primary

  using address translation or modifications · CPC title

• G11C29/78

  using programmable devices · CPC title