Apparatuses and methods for flexible fuse transmission

Patent metadata

Field	Value
Publication number	US-9666307-B1
Application number	US-201615265671-A
Country	US
Kind code	B1
Filing date	Sep 14, 2016
Priority date	Sep 14, 2016
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

First claim

What is claimed is:

1. An apparatus comprising:
a bus;
a plurality of latches coupled to the bus and configured to be activated one-by-one, wherein an activated latch of the plurality of latches is configured to capture data on the bus; and
a control circuit configured to provide the bus with valid data when a first latch of the plurality of latches is activated and further configured to provide the bus with invalid data when a second latch of the plurality of latches is activated.

2. The apparatus as claimed in claim 1 ,
wherein the control circuit is configured to receive a plurality of input data, each input data of the plurality of input data including a data portion and a token portion, and
wherein the control circuit is configured to provide the bus with the valid data corresponding to the data portion when the token portion has a first state and further configured to provide the bus with the invalid data when the token portion has a second state.

3. The apparatus as claimed in claim 2 , wherein the second state of the token portion indicates a number of latches capturing the invalid data.

4. The apparatus as claimed in claim 1 , wherein the control circuit is configured to provide the bus with the valid data and the invalid data alternately.

5. The apparatus as claimed in claim 3 , wherein the number of latches indicated by the token portion is more than one, and wherein the data portion associated with the token portion having the second state is captured as the valid data by a latch of the plurality of latches that is to be activated subsequently to latches of the plurality of latches having been activated by the number indicated by the second state of the token portion.

6. The apparatus as claimed in claim 4 ,
wherein the control circuit is configured to receive a plurality of pairs of input data, and
wherein the control circuit is configured, with respect to each of the plurality of pairs of input data, to provide the bus with the valid data and the invalid data alternately, the valid data being derived by performing one of a logical OR operation and a logical AND operation on a corresponding one of the plurality of pairs of input data.

7. The apparatus of claim 5 , wherein the control circuit is further configured to provide redundant error detection information on the bus prior to providing data including defective addresses on the bus, and
wherein the redundant error detection information is related to a cell for redundancy data that is defective.

8. An apparatus comprising:
a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data;
a fuse circuit configured to receive the input data, and further configured to provide the input data on a bus; and
a plurality of redundancy latch circuits coupled to the bus, comprising a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers and configured to load data on the bus;
wherein the fuse circuit is configured to control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

9. The apparatus of claim 8 , wherein the input data comprise a defective address and a token representing a number of pointers to be skipped, and
wherein the fuse circuit is configured to provide invalid data to latches among the plurality of latches corresponding to the number of pointers to be skipped and further configured to provide valid data to a latch among the plurality of latches corresponding to a pointer next to the number of pointers to be skipped.

10. The apparatus of claim 9 , wherein each redundancy latch circuit of the plurality of redundancy latch circuits comprises a first redundancy latch group comprising a plurality of first latches configured to load and a plurality of first pointers associated with the plurality of first latches and a second redundancy latch group comprising a plurality of second latches and a plurality of second pointers associated with the plurality of second latches, and
wherein the first pointers in the first redundancy latch groups of the plurality of redundancy latch circuits are coupled in series in a first chain and the second pointers of the second redundancy latch groups of the plurality of redundancy latch circuits are coupled in series in a second chain.

11. The apparatus of claim 8 ,
wherein a plurality of consecutive fuse arrays in the plurality of fuse arrays are configured to store an identical defective address;
wherein the fuse circuit is configured to read data from the plurality of consecutive fuse arrays and further configured to provide a logical sum of the data from the plurality of consecutive fuse arrays.

12. The apparatus of claim 8 , wherein each fuse array of the plurality of fuse arrays is configured to store input data including a defective address and a token representing bank information associated with the defective address, and
wherein the fuse circuit comprises a decoder configured to provide an enable signal or a disable signal for each bank responsive to the bank information from each fuse array.

13. The apparatus of claim 12 , wherein the bank information is indicative of a relationship between a bank identification number of a current fuse array and a bank identification number of a next fuse array, and
wherein the fuse circuit further comprises a counter configured to store a bank identification number of a current fuse array and configured to compute the bank identification number of the current fuse array to obtain the bank identification number of a next fuse array responsive to the bank information.

14. The apparatus of claim 8 , wherein the plurality of fuse arrays are further configured to store redundant error detection information related to a cell for redundancy data that is defective,
wherein the fuse circuit is further configured to provide redundant error detection information on the bus prior to providing data including defective addresses on the bus, and
each redundancy latch circuit of the plurality of redundancy latch circuits further comprises a plurality of error detect latches corresponding to the plurality of latches, the plurality of error detect latches are configured to disable the corresponding plurality of latches responsive to the redundant error detection information on the bus, prior to receiving the data including defective addresses on the bus.

15. A method of transmitting fuse data, comprising:
receiving input data stored in a fuse array;
controlling a location of a pointer responsive to the input data;
providing the input data on a bus; and
loading the input data on the bus into a latch associated with the pointer among a plurality of latches coupled to the bus.

16. The method of claim 15 , wherein the input data comprise a defective address and a token representing a number of pointers to be skipped, the method further comprising:
providing invalid data to latches among the plurality of latches corresponding to the number of pointers to be skipped; and
providing valid data to a latch among the plurality of latches corresponding to a pointer next to the number of pointers to be skipped.

17. The method of claim 15 , wherein the plurality of latches includes:
a first group of latches associated with a first group of pointers across banks coupled in series in a first chain; and
a second group of latches associated with a second group of pointers across banks coupled in series in a second chain,
the method further compri

Assignees

• Micron Technology Inc

Inventors

• Fujiwara Yoshinori
• Yoshida Kenji
• Someya Minoru
• Noda Hiromasa

Classifications

• G11C29/785 Primary

  with redundancy programming schemes · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C29/76 Primary

  using address translation or modifications · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title