Managing threshold voltage shift in nonvolatile memory

Patent metadata

Field	Value
Publication number	US-10056139-B2
Application number	US-201715645990-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Apr 2, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.

First claim

What is claimed is:

1. A memory controller, comprising circuitry configured to:
receive an input/output (I/O) request referenced to a memory location of a non-volatile memory (NVM) device;
obtain a compensated demarcation voltage (Vdm) by either a time-based drift compensation mode or a disturb-based drift compensation mode;
determine if the I/O request is a read request or a write request;
if the I/O request is a read request, apply the compensated Vdm to a memory cell of the memory location; and
if the I/O request is a write request, apply a programming pulse to a memory cell of the memory location, the programming pulse having a voltage greater than the compensated Vdm.

2. The memory controller of claim 1 , wherein to obtain the compensated Vdm by the time-based drift compensation mode, the circuitry is further configured to:
determine a time elapsed since a last write operation to the memory cell of the memory location; and
determine the compensated Vdm using the time elapsed.

3. The memory controller of claim 2 , wherein to determine the compensated Vdm, the circuitry is further configured to:
compare the time elapsed to a plurality of elapsed time subranges correlated with a plurality of potential compensated Vdms;
select an elapsed time subrange from the plurality of elapsed time subranges that includes the time elapsed; and
identify the potential compensated Vdm associated with the selected elapsed time subrange as the compensated Vdms.

4. The memory controller of claim 1 , wherein to obtain the compensated Vdm by the disturb-based drift compensation mode, the circuitry is further configured to:
receive a read or a write operation referenced to the memory location;
determine a number of disturbs to the memory cell since a last write to the memory cell; and
determine the compensated Vdm using the number of disturbs.

5. The memory controller of claim 4 , wherein to determine the compensated Vdm, the circuitry is further configured to:
compare the number of disturbs to a plurality of disturb number subranges correlated with a plurality of potential compensated Vdms;
select a disturb number subrange from the plurality of disturb number subranges that includes the number of disturbances to the memory cell; and
identify the potential compensated Vdm associated with the selected disturb number subrange as the compensated Vdms.

6. The memory controller of claim 4 , wherein the number of disturbs comprises a number of read operations to the memory cell.

7. The memory controller of claim 1 , wherein the circuitry further comprises:
a mode indicator configured to specify whether the compensated Vdm is obtained according to the time-based drift compensation mode or the disturb-based drift compensation mode.

8. The memory controller of claim 7 , wherein the mode indicator is a mode bit.

9. The memory controller of claim 7 , wherein the memory cell comprises a phase change memory (PCM) cell.

10. The memory controller of claim 1 , wherein the NVM device comprises a three-dimensional (3D) cross-point array.

11. A memory computation system, comprising:
at least one processor;
a non-volatile memory (NVM) device comprising an array of memory cells; and
a controller coupled to the NVM device and the at least one processor, the controller further comprising circuitry configured to:
receive an input/output (I/O) request referenced to a memory location of the NVM device;
determine whether a compensated demarcation voltage (Vdm) is to be obtained according to a time-based drift compensation mode or a disturb-based drift compensation mode;
obtain the compensated Vdm according to the determined mode;
determine if the I/O request is a read request or a write request;
if the I/O request is a read request, apply the compensated Vdm to a memory cell of the memory location of the array of memory cells; and
if the I/O request is a write request, apply a programming pulse to a memory cell of the memory location, the programming pulse having a voltage greater than the compensated Vdm.

12. The computation system of claim 11 , further comprising a mode indicator coupled to the controller and configured to specify whether the compensated Vdm is obtained according to the time-based drift compensation mode or the disturb-based drift compensation mode.

13. The computation system of claim 11 , wherein to obtain the compensated Vdm by the time-based drift compensation mode, the circuitry is further configured to:
receive a read or a write operation referenced to the memory location;
determine a time elapsed since a last write operation to the memory cell of the memory location; and
determine the compensated Vdm using the time elapsed.

14. The computation system of claim 13 , wherein to determine the compensated Vdm, the circuitry is further configured to:
compare the time elapsed to a plurality of elapsed time subranges correlated with a plurality of potential compensated Vdms;
select an elapsed time subrange from the plurality of elapsed time subranges that includes the time elapsed; and
identify the potential compensated Vdm associated with the selected elapsed time subrange as the compensated Vdms.

15. The computation system of claim 11 , wherein to obtain the compensated Vdm by the disturb-based drift compensation mode, the circuitry is further configured to:
receive a read or a write operation referenced to the memory location;
determine a number of disturbs to the memory cell since a last write to the memory cell; and
determine the compensated Vdm using the number of disturbs.

16. The computation system of claim 15 , wherein to determine the compensated Vdm, the circuitry is further configured to:
compare the number of disturbs to a plurality of disturb number subranges correlated with a plurality of potential compensated Vdms;
select a disturb number subrange from the plurality of disturb number subranges that includes the number of disturbs to the memory cell; and
identify the potential compensated Vdm associated with the selected disturb number subrange as the compensated Vdms.

17. The computation system of claim 11 , wherein the array of memory cells includes an array of phase change memory (PCM) cells.

18. The computation system of claim 17 , wherein the array of PCM cells is configured as a three-dimensional (3D) cross-point array.

19. The computation system of claim 11 , further comprising one or more of:
a network interface communicatively coupled to the at least one processor;
a display communicatively coupled to the at least one processor; or
a power supply communicatively coupled to the at least one processor.

Assignees

• Intel Corp

Inventors

• Qawami Shekoufeh
• Sundaram Rajesh
• Damle Prashant S
• Rivers Doyle
• Walker Julie M

Classifications

• G11C13/0033 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title