Techniques for maintaining atomicity and ordering for pixel shader operations

Patent metadata

Field	Value
Publication number	US-10055806-B2
Application number	US-201514924618-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Oct 27, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

First claim

What is claimed is:

1. A graphics subsystem configured to generate tiles of coverage samples, the subsystem comprising:
a first bin buffer that collects arrays of coverage samples associated with a first range of X-Y values; and
a tile engine that is coupled to the first bin buffer and:
drains a first array of coverage samples from the first bin buffer,
compares the first array of coverage samples to a tile mask to determine that a first tile does not yet include a coverage sample at a first X-Y position, and
inserts a first coverage sample included in the first array of coverage samples into the first tile.

2. The graphics subsystem of claim 1 , wherein the tile engine inserts the first coverage sample into the first tile by:
generating a second array of coverage samples that includes the first coverage sample; and
inserting the second array of coverage samples into the first tile.

3. The graphics subsystem of claim 1 , wherein the tile engine further updates the tile mask to indicate that the tile mask includes the first coverage sample at the first X-Y position.

4. The graphics subsystem of claim 1 , wherein the tile engine further:
compares the first array of coverage samples to the tile mask to determine that the first tile already includes a coverage sample at a second X-Y position; and
re-circulates a second coverage sample included in the first array of coverage samples.

5. The graphics subsystem of claim 4 , wherein the tile engine re-circulates the second coverage sample by:
generating a second array of coverage samples that includes the second coverage sample; and
placing the second array of coverage samples into the first bin buffer for processing in conjunction with a subsequent tile.

6. The graphics subsystem of claim 4 , wherein the tile engine further updates the tile mask to indicate that the second coverage sample was recirculated.

7. The graphics subsystem of claim 4 , wherein the first coverage sample is associated with a first quad of pixels or samples, and the second coverage sample is associated with a second quad of pixels or samples.

8. The graphics subsystem of claim 4 , wherein the first coverage sample is associated with a first pixel or sample, the second coverage sample is associated with a second pixel or sample, and the first pixel or sample resides adjacent to the second pixel or sample.

9. The graphics subsystem of claim 1 , wherein the first range of X-Y values comprises an X-Y range of screen space, and the first array of coverage samples has X-Y dimensions that are less than the first range of X-Y values.

10. The graphics subsystem of claim 1 , wherein the tile engine further generates a second tile that includes a second coverage sample at the first X-Y position, wherein the first coverage sample appears before the second coverage sample in an application programming interface order.

11. The graphics subsystem of claim 10 , wherein the tile engine further:
issues the first tile to a downstream unit, wherein the downstream unit is executed by a parallel processor; and
issues the second tile to the downstream unit, wherein the downstream unit receives the first tile and the second tile in the application programming interface order associated with coverage samples.

12. The graphics subsystem of claim 11 , wherein the downstream unit:
assigns a first thread group to perform one or more programmable blending operations with the first tile; and
assigns a second thread group to perform the one or more programmable blending operations with the second tile,
wherein the first thread group and the second thread group perform the one or more programmable blending operations according to the application programming interface order.

13. A computer-implemented method for generating tiles of coverage samples, the method comprising:
collecting arrays of coverage samples associated with a first range of X-Y values into a first bin;
draining a first array of coverage samples from the first bin;
comparing the first array of coverage samples to a tile mask to determine that a first tile does not yet include a coverage sample at a first X-Y position; and
inserting a first coverage sample included in the first array of coverage samples into the first tile.

14. The computer-implemented method of claim 13 , wherein inserting the first coverage sample into the first tile comprises:
generating a second array of coverage samples that includes the first coverage sample; and
inserting the second array of coverage samples into the first tile.

15. The computer-implemented method of claim 13 , further comprising:
comparing the first array of coverage samples to the tile mask to determine that the first tile already includes a coverage sample at a second X-Y position; and
re-circulating a second coverage sample included in the first array of coverage samples.

16. The computer-implemented method of claim 15 , wherein re-circulating the second coverage sample comprises:
generating a second array of coverage samples that includes the second coverage sample; and
placing the second array of coverage samples into the first bin for processing in conjunction with a subsequent tile.

17. The computer-implemented method of claim 16 , wherein the first tile and the subsequent tile are processed in an application programming interface order associated with the first coverage sample and the second coverage sample.

18. A computing device, comprising:
a raster unit that generates coverage samples, wherein the raster unit is executed by a parallel processor; and
a graphics subsystem, including:
a first bin buffer that collects arrays of coverage samples associated with a first range of X-Y values, and
a tile engine that is coupled to the first bin buffer and:
drains a first array of coverage samples from the first bin buffer,
compares the first array of coverage samples to a tile mask to determine that a first tile does not yet include a coverage sample at a first X-Y position, and
inserts a first coverage sample included in the first array of coverage samples into the first tile.

19. The computing device of claim 18 , wherein the tile engine inserts the first coverage sample into the first tile by:
generating a second array of coverage samples that includes the first coverage sample; and
inserting the second array of coverage samples into the first tile.

20. The computing device of claim 18 , wherein the tile engine further:
compares the first array of coverage samples to the tile mask to determine that the first tile already includes a coverage sample at a second X-Y position; and
re-circulates a second coverage sample included in the first array of coverage samples.

21. The computing device of claim 18 , further comprising:
a thread management unit that:
receives the first tile, and
receives a second tile that includes a second coverage sample, wherein the thread management unit is executed by a parallel processor,
wherein the thread management unit receives the first tile and the second tile in an application programming interface order associated with the first coverage sample and the second coverage sample.

22. The computing device of claim 21 , wherein the thread management unit:
assigns a first thread group to perform one or more programmable blending operations with the first tile; and
assigns a second thread group to perform the one or more programmable blending operations with the second tile,
wherein

Assignees

• Nvidia Corp

Inventors

• Hakura Ziyad
• Lum Eric
• Kirkland Dale
• Choquette Jack
• Brown Patrick R
• Uralsky Yury Y
• Bolz Jeffrey

Classifications

• G06T11/40 Primary

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

• G06T1/60

  Memory management · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title