Optimizing shading process for mixed order-sensitive and order-insensitive shader operations

Patent metadata

Field	Value
Publication number	US-2016307365-A1
Application number	US-201514687832-A
Country	US
Kind code	A1
Filing date	Apr 15, 2015
Priority date	Apr 15, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

A graphics processing unit (GPU) includes programmable shader hardware and grouping hardware. The grouping hardware receives pixels collected from a set of primitives, wherein pixel locations of each primitive have been obtained through rasterization of a set of vertices of the primitive. The grouping hardware also groups the pixels into a set of groups having a sequential order. None of the pixels in each group overlapped with each other in a display and overlapped pixels belong to different groups. The programmable shader hardware performs order-insensitive shader operations on the groups according to a first subset of an instruction set defined for a programmable shader, with two or more of the groups processed in parallel. The programmable shader hardware also performs order-sensitive shader operations on each of the groups in the sequential order according to a second subset of the instruction set defined for the programmable shader.

First claim

What is claimed is:

1 . A method of a Graphics Processing Unit (GPU) comprising:
receiving pixels collected from a set of primitives, wherein pixel locations of each primitive have been obtained through rasterization of a set of vertices of the primitive; grouping the pixels into a set of groups having a sequential order, wherein none of the pixels in each group overlapped with each other in a display and overlapped pixels belong to different groups; performing order-insensitive shader operations on the groups according to a first subset of an instruction set defined for a programmable shader, with two or more of the groups processed in parallel; and performing order-sensitive shader operations on each of the groups in the sequential order according to a second subset of the instruction set defined for the programmable shader.

2 . The method of claim 1 , wherein the overlapped pixels in the different groups follow the sequential order defined by a graphics application program interface (API) requirement that specifies an API order of sequencing the primitives for rendering.

3 . The method of claim 2 , wherein a primitive sequenced after a second group according to the API order is placed in a first group before the second group if the primitive does not overlap with any other primitives in the first group and the second group.

4 . The method of claim 1 , wherein the order-insensitive operations include fragment shader operations, and the order-sensitive operations include alpha blending.

5 . The method of claim 4 , further comprising:
executing an intergroup barrier on each group after the fragment shader operations to order the groups in the sequential order for the alpha blending.

6 . The method of claim 5 , wherein the group includes a first group and a second group, the method further comprising:
performing the fragment shader operations on the first group and the second group; and stalling the second group with the intergroup barrier when performing the blending operations on the first group.

7 . The method of claim 4 , further comprising:
executing an instruction that specifies a blending mode register to select a shader code segment for a pre-defined blending mode.

8 . The method of claim 1 , wherein performing the order-sensitive operations further comprises:
performing the order-sensitive operations in an arbitrary order on the pixels within each of the groups.

9 . The method of claim 1 , wherein the order-sensitive operations include depth testing to resolve visibility of the pixels across different groups.

10 . The method of claim 1 , wherein performing the order-sensitive operations further comprises:
performing alpha blending on a set of pixels that include at least one of: transparent pixels, opaque pixels, and a combination of transparent pixels and opaque pixels.

11 . A Graphics Processing Unit (GPU) comprising:
grouping hardware to receive pixels collected from a set of primitives, wherein pixel locations of each primitive have been obtained through rasterization of a set of vertices of the primitive, and to group the pixels into a set of groups having a sequential order, wherein none of the pixels in each group overlapped with each other in a display and overlapped pixels belong to different groups, programmable shader hardware coupled to the grouping hardware and including an array of computing units, the programmable shader hardware operative to:
perform order-insensitive shader operations on the groups according to a first subset of an instruction set defined for a programmable shader, with two or more of the groups processed in parallel; and
perform order-sensitive shader operations on each of the groups in the sequential order according to a second subset of the instruction set defined for the programmable shader.

12 . The GPU of claim 11 , wherein the overlapped pixels in the different groups follow the sequential order defined by a graphics application program interface (API) requirement that specifies an API order of sequencing the primitives for rendering.

13 . The GPU of claim 12 , wherein a primitive sequenced after a second group according to the API order is placed in a first group before the second group if the primitive does not overlap with any other primitives in the first group and the second group.

14 . The GPU of claim 11 , wherein the order-insensitive operations include fragment shader operations, and the order-sensitive operations include alpha blending.

15 . The GPU of claim 14 , wherein the programmable shader hardware is further operative to execute an intergroup barrier on each group after the fragment shader operations to order the groups in the sequential order for the alpha blending.

16 . The GPU of claim 15 , wherein the group includes a first group and a second group, and wherein the programmable shader hardware is further operative to:
perform the fragment shader operations on the first group and the second group; and stall the second group with the intergroup barrier when performing the blending operations on the first group.

17 . The GPU of claim 14 , wherein the programmable shader hardware is further operative to execute an instruction that specifies a blending mode register to select a shader code segment for a pre-defined blending mode.

18 . The GPU of claim 11 , wherein the programmable shader hardware is further operative to perform the order-sensitive operations in an arbitrary order on the pixels within each of the groups.

19 . The GPU of claim 11 , wherein the order-sensitive operations include depth testing to resolve visibility of the pixels across different groups.

20 . The GPU of claim 11 , wherein the programmable shader hardware is further operative to perform alpha blending on a set of pixels that include at least one of: transparent pixels, opaque pixels, and a combination of transparent pixels and opaque pixels.

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Liao Qun-Feng
• Ko Cheng-Ying

Classifications

• G06T15/83 Primary

  Phong shading · CPC title

• G06T15/20

  Perspective computation · CPC title

• G06T15/503

  Blending, e.g. for anti-aliasing · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title