Method, system and program product for identifying anomalies in integrated circuit design layouts

Patent metadata

Field	Value
Publication number	US-10055535-B2
Application number	US-201615277796-A
Country	US
Kind code	B2
Filing date	Sep 27, 2016
Priority date	Sep 27, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database. The method further includes determining one or more feature attributes for each of the plurality of unit-level geometric constructs, annotating the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs, mapping the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane, applying a first model to the mapped hyperplane, identifying the anomalies from applying the first model, and applying a second model to the mapped hyperplane to rank the anomalies for printability risk, the generated data including rank data.

First claim

The invention claimed is:

1. A method, comprising:
providing a data representation of at least one integrated circuit design layout and one or more input parameters to a memory in communication with a processor;
deconstructing, by the processor according to instructions stored in the memory, the data representation into a plurality of unit-level geometric constructs;
identifying, by the processor according to instructions stored in the memory, anomalies in the plurality of unit-level geometric constructs, wherein the identifying is based on only the plurality of unit-level geometric constructs;
storing, by the processor according to instructions stored in the memory, anomaly data in a database, wherein the providing, the deconstructing, the identifying and the storing are performed prior to semiconductor manufacturing; and
using the anomaly data to perform semiconductor manufacturing, the using improving semiconductor manufacturing yield as compared to not using the anomaly data.

2. The method of claim 1 , wherein the identifying comprises:
determining, by the processor according to instructions stored in the memory, one or more feature attributes for each of the plurality of unit-level geometric constructs; and
annotating, by the processor according to instructions stored in the memory, the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs.

3. The method of claim 2 , further comprising mapping, by the processor according to instructions stored in the memory, the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane.

4. The method of claim 3 , further comprising:
applying, by the processor according to instructions stored in the memory, a first model to the mapped hyperplane; and
identifying, by the processor according to instructions stored in the memory, the anomalies from applying the first model.

5. The method of claim 4 , wherein the first model comprises at least one of a filtering model and an anomaly-detection model.

6. The method of claim 4 , further comprising applying, by the processor according to instructions stored in the memory, a second model to the mapped hyperplane to rank the anomalies for patterning risk, wherein an outcome of applying the second model comprises rank data.

7. The method of claim 6 , wherein the second model comprises at least one of a process-based simulation and a scoring model.

8. The method of claim 6 , wherein applying the second model further comprises validating, by the processor according to instructions stored in the memory, the anomalies.

9. A system, comprising:
a memory; and
at least one processor in communication with the memory, the memory storing instructions to perform a method, the method comprising:
providing, by the at least one processor according to the instructions, a data representation of at least one integrated circuit design layout;
deconstructing, by the at least one processor according to the instructions, the data representation into a plurality of unit-level geometric constructs;
identifying, by the at least one processor according to the instructions, anomalies in the plurality of unit-level geometric constructs, wherein the identifying is based on only the plurality of unit-level geometric constructs;
storing, by the at least one processor according to the instructions, anomaly data in a database, wherein the providing, the deconstructing, the identifying and the storing are performed prior to semiconductor manufacturing; and
using the anomaly data to perform semiconductor manufacturing, the using improving semiconductor manufacturing yield as compared to not using the anomaly data.

10. The system of claim 9 , wherein the identifying comprises:
determining, by the at least one processor according to the instructions, one or more feature attributes for each of the plurality of unit-level geometric constructs; and
annotating, by the at least one processor according to the instructions, the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs.

11. The system of claim 10 , further comprising mapping, by the at least one processor according to the instructions, the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane.

12. The system of claim 11 , further comprising:
applying, by the at least one processor according to the instructions, a first model to the mapped hyperplane; and
identifying, by the at least one processor according to the instructions, the anomalies from applying the first model.

13. The system of claim 12 , wherein the first model comprises at least one of a filtering model and an anomaly-detection model, and wherein the method further comprises applying, by the at least one processor according to the instructions, a second model to the mapped hyperplane to rank the anomalies for patterning risk, wherein the generated data comprises rank data.

14. The system of claim 13 , wherein the second model comprises at least one of a process-based simulation and a scoring model, and wherein applying the second model further comprises validating, by the at least one processor according to the instructions, the anomalies.

15. A computer program product, comprising:
a non-transitory storage medium readable by a processor and storing instructions for execution by the processor for performing a method, the method comprising:
providing a data representation of at least one integrated circuit design layout and one or more input parameters to a memory in communication with the processor;
deconstructing, by the processor according to the instructions, the data representation into a plurality of unit-level geometric constructs;
identifying, by the processor according to the instructions, anomalies in the plurality of unit-level geometric constructs, wherein the identifying is based on only the plurality of unit-level geometric constructs;
storing, by the processor according to the instructions, anomaly data in a database, wherein the providing, the deconstructing, the identifying and the storing are performed prior to semiconductor manufacturing; and
using the anomaly data to perform semiconductor manufacturing, the using improving semiconductor manufacturing yield as compared to not using the anomaly data.

16. The computer program product of claim 15 , wherein the identifying comprises:
determining, by the processor according to the instructions, one or more feature attributes for each of the plurality of unit-level geometric constructs; and
annotating, by the processor according to the instructions, the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs.

17. The computer program product of claim 16 , further comprising mapping, by the processor according to the instructions, the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, the mapping resulting in a mapped hyperplane.

18. The computer program product of claim 17 , further comprising:
applying, by the processor according to the instructions, a first model to th

Assignees

• Globalfoundries Inc

Inventors

• Pathak Piyush
• Pack Robert C
• Wang wei-long
• Krishnamoorthy Karthik
• Batarseh Fadi S
• Schroeder Uwe Paul
• Madhavan Sriram

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G03F7/70433 Primary

  Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors · CPC title

• G06F2217/12

  Physics · mapped topic