Generative learning for realistic and ground rule clean hot spot synthesis

Patent metadata

Field	Value
Publication number	US-2016378902-A1
Application number	US-201514749909-A
Country	US
Kind code	A1
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.

First claim

What is claimed is:

1 . A semiconductor device design layout generation computer program product stored on non-transitory computer readable storage media in the form of computer executable code including instructions that when executed by a computing device cause the computing device to perform a method comprising:
applying a generative model to generate a plurality of candidate layout images based on at least a feature library including features extracted from known layouts, the features being represented by respective feature images in a first colorspace and the plurality of candidate layout images being in a second colorspace; ranking the plurality of candidate layout images based on a first difference value representing a degree of difference between each candidate layout image and the feature images in the feature library; removing any candidate layout image having a first difference value below a predefined minimum first difference threshold to form a culled group of candidate layout images; performing a repair procedure on the culled group to produce a plurality of compliant candidate layout images in the first colorspace; and ranking the plurality of clean candidate layout images based at least in part on a respective second difference value representing a degree of difference between each clean candidate layout image and the feature images of the feature library.

2 . The computer program product of claim 1 , wherein the applying a generative model to generate a plurality of candidate layout images in the second colorspace includes, for each candidate layout image:
sampling from the feature library to obtain a plurality of initial layouts in the first colorspace; determining a respective probability of success of each initial layout; and combining the selected layout images to form a candidate layout image including a probabilistic layout image in the second colorspace, the second colorspace having at least one channel in which each pixel includes a respective channel value that represents a combined probability of success of pixels from the selected layout images.

3 . The computer program product of claim 1 , wherein the first difference value is a mathematical distance and the ranking of the plurality of candidate layout images includes determining a respective mathematical distance value for each candidate layout image using L 2 norm comparison.

4 . The computer program product of claim 3 , wherein the mathematical distance includes at least one of a Euclidean distance, a Hamming distance, a Mahalanobis distance, and a Manhattan distance.

5 . The computer program product of claim 1 , wherein the performing of the repair procedure on the culled group includes thresholding a respective channel value of each pixel using a predefined threshold channel value so that each pixel having a channel value above the threshold channel value is converted to a first color value of the first colorspace, and each pixel having a channel value below the threshold channel value is converted to a second color value of the first colorspace.

6 . The computer program product of claim 1 , wherein the applying of the generative model includes generating the candidate layout images using at least one probability density function of the generative model to obtain the candidate layout images in the second colorspace, and the second colorspace includes at least one channel in which each pixel has a value representing a probability of the respective pixel.

7 . The computer program product of claim 6 , wherein the performing of the repair procedure on the culled group includes reconstructing from each candidate layout image at least one downconverted candidate image in the first colorspace.

8 . The computer program product of claim 7 , wherein the performing of the repair procedure further includes determining a normalized design rule error {right arrow over (ε DRC )} of each layout π of the plurality of candidate layouts based at least in part on the relationship:

ɛ
DRC

→

=

[

ɛ
1
DRC



(
π
)

⋮

ɛ
n
DRC



(
π
)

]




for



0

≤

π


(

i
,
j

)

≤
1

,

i
∈

[

1
,
A

]

,

j
∈

[

1
,
B

]

where n is a number of rules applied to a current layout, A and B are length and width of the layout.

9 . The computer program product of claim 8 , wherein the performing of the repair procedure further includes minimizing the normalized error based at least in part on the relationship:
min{right arrow over (ε DRC )}(π)=LithoDiff(π),

where LithoDiff is a measure of a respective photolithographic difficulty associated with each pattern π.

10 . A method of semiconductor device design layout generation comprising:
applying a generative model to generate a plurality of candidate layouts based on at least a feature library of features extracted from known layouts and represented in a first colorspace, each candidate layout: including a

Assignees

• Globalfoundries Inc

Inventors

• Graur Ioana C
• Stobert Ian P
• Vengertsev Dmitry A

Classifications

• G03F1/36

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5077

  Physics · mapped topic