Automated checker generation

Patent metadata

Field	Value
Publication number	US-10055522-B2
Application number	US-201615174075-A
Country	US
Kind code	B2
Filing date	Jun 6, 2016
Priority date	Jun 6, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

The invention relates to a method for verifying a design of an electronic circuit. The electronic circuit comprises at least one register including one or more parts. After receiving specification information of said register, a register monitor module is automatically created based on said received specification information. The register monitor module comprises a scoreboard for each part of the register. Said scoreboard comprises an expected data value queue for receiving expected data values, an actual data value queue for receiving actual data values. Furthermore, the register monitor module provides a matching strategy for comparing expected data values with actual data values. Expected data values and actual data values are compared for each scoreboard based on the matching strategy and an error indication is generated if the result of the comparison step does not fulfill the requirements specified in the matching strategy.

First claim

The invention claimed is:

1. A computer-implemented method for verifying a design of an electronic circuit including a register, the method comprising:
receiving specification information of a register, said specification information comprising information regarding the parts included in the register;
automatically generating a register monitor module based on said received specification information, said register monitor module comprising a scoreboard for each part of the register, said scoreboard comprising an expected data value queue for receiving expected data values which are expected to be included in the respective part of the register and an actual data value queue for receiving actual data values actually included in the respective part of the register, the register monitor module further including a matching strategy for comparing expected data values with actual data values;
detecting a change to the register;
responsive to detecting a change to the register, calculating one or more actual data values using a simulation environment simulating the electronic circuit and providing said one or more actual data values to the actual data value queue of the respective scoreboard;
calculating one or more expected data values corresponding to the one or more actual data values using a reference model of the electronic circuit and providing said expected data values to the expected data value queue of the respective scoreboard;
comparing, for the respective scoreboard, a first actual data value from the actual data value queue to a first expected data value from the expected data value queue according to the matching strategy to determine whether the first actual data value and the first expected data value match;
responsive to determining that the first actual data value and the first expected data value match, removing the first actual data value from the actual data value queue and removing the first expected data value from the expected data value queue; and
responsive to determining that the result of the comparison step does not fulfill the requirements specified in the matching strategy, generating an error indication.

2. The computer-implemented method according to claim 1 , wherein certain specification values are extracted from said specification information and the register monitor module is adaptively generated based on said extracted specification values.

3. The computer-implemented method according to claim 2 , wherein information regarding the number of parts included in the register and information regarding the size of the respective parts is extracted.

4. The computer-implemented method according to claim 1 , wherein the register monitor module is generated including a number of scoreboards equal to the number of parts included in the register.

5. The computer-implemented method according to claim 1 , wherein each scoreboard is associated with a scoreboard-inherent matching strategy and the comparison of actual data values with expected data values and the generation of an error indication are based on said scoreboard-inherent matching strategy.

6. The computer-implemented method according to claim 1 , wherein the matching strategy is a customizable matching strategy indicating the matching requirements to be fulfilled when comparing values of the expected data value queue with values of the actual data value queue.

7. The computer-implemented method according to claim 1 , wherein expected data values are provided by a unit monitor module, said unit monitor module receiving information regarding the input data and output data of the simulation environment of the electronic circuit and providing expected data values based on the reference model of the simulated electronic circuit and said input data and output data.

8. The computer-implemented method according to claim 1 , wherein the simulation environment of the electronic circuit provides actual data values of a part of the register to the scoreboard associated with said part.

9. The computer-implemented method according to claim 1 , wherein the register monitor module detects changes of actual data values within a part of the register and provides said changed actual data values to the scoreboard associated with said part of the register.

10. A computer system for verifying a design of an electronic circuit including a register, the system comprising:
an input interface for receiving specification information of a register, said specification information comprising information regarding the parts included in the register;
a generation module being adapted to automatically generate a register monitor module based on said received specification information, said register monitor module comprising a scoreboard for each part of the register, said scoreboard comprising an expected data value queue for receiving expected data values which are expected to be included in the respective part of the register, an actual data value queue for receiving actual data values actually included in the respective part of the register, the register monitor module further including a matching strategy for comparing expected data values with actual data values;
a unit monitor module configured to detect a change to the register and to, responsive to detecting a change to the register, calculate expected data values using a reference model of the electronic circuit and to provide said expected data values to the expected data value queue of the respective scoreboard;
a simulation module configured to, responsive to detecting a change to the register, calculate one or more actual data values by simulating the electronic circuit and providing said one or more actual data values to the actual data value queue of the respective scoreboard;
a comparator module configured to compare, for the respective scoreboard, a first actual data value from the actual data value queue to a first expected data value from the expected data value queue according to the matching strategy to determine whether the first actual data value and the first expected data value match based on the matching strategy; and
an output interface for providing an error indication if the result provided by the comparator does not fulfil the requirements specified in the matching strategy and to remove the first actual data value from the actual data value queue and remove the first expected data value from the expected data value queue if the first actual data value and the first expected data value match.

11. The computer system according to claim 10 , comprising extraction means for extracting certain specification values from said specification information, wherein the generation module is configured to adaptively generate said register monitor module based on said extracted specification values.

12. The computer system according to claim 11 , wherein said extraction means are configured to extract information regarding the number of parts included in the register and information regarding the size of the respective parts.

13. The computer system according to claim 12 , wherein said generation module is configured to provide a register monitor module including a plurality of scoreboards, the number of scoreboards being equal to the extracted number of parts included in the register.

14. The computer system according to claim 10 , wherein the unit monitor module is configured to receive information regarding the input data and output data of the simulated electronic circuit and configured to calculate expected data values based on the reference model of the simulated electronic circuit and said input data and output data.

Assignees

• IBM

Inventors

• Behrend Joerg
• Horbach Holger
• Jung Alexander
• Keuerleber Klaus
• Sentler Daniel D
• Wakunda Jurgen

Classifications

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F17/5009 Primary

  Physics · mapped topic

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3308

  using simulation · CPC title