Joint encryption and error correction encoding

Patent metadata

Field	Value
Publication number	US-10050645-B2
Application number	US-201415114501-A
Country	US
Kind code	B2
Filing date	Jan 30, 2014
Priority date	Jan 30, 2014
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A technique includes jointly encrypting and error encoding plain text data. The joint encryption and error encoding includes processing plain text data in an encryption cipher comprising a plurality of successive rounds to generate cipher text data; and embedding error correction encoding in the encryption cipher to error correction encode the cipher text data.

First claim

What is claimed is:

1. A method comprising:
with a hardware memory controller, jointly encrypting and error encoding plain text data to generate cipher text data, comprising:
processing, with the hardware memory controller, the plain text data with an encryption cipher comprising a plurality of successive rounds, the plurality of successive rounds including a final round; and
with the hardware memory controller, interleaving error correction encoding within the encryption cipher prior to a stage of the final round associated with a linear substitution to error correction encode the generated cipher text data.

2. The method of claim 1 , wherein at least one of the plurality of successive rounds other than the final round comprises a diffusion transformation.

3. The method of claim 1 , wherein interleaving the error correction encoding comprises performing error correction encoding in the final round before a SubBytes transformation in the final round.

4. The method of claim 1 , wherein processing the plain text data with an encryption cipher comprises using multiple long keys.

5. The method of claim 1 , wherein the error correction encoding generates parity codewords, the method further comprising:
generating a first mask based at least in part on a cipher key; and
exclusive ORing the parity codewords with the first mask.

6. The method of claim 5 , further comprising:
processing a result of the exclusive ORing with a second mask.

7. A method comprising:
with a hardware memory controller, processing cipher text data with a decryption cipher comprising a plurality of successive rounds to generate plain text data; and
in the decryption cipher, extracting error correction data for the plain text data with the hardware memory controller during a temporary suspension of inverse transformations in one of the plurality of successive rounds.

8. The method of claim 7 , wherein the plurality of successive rounds comprise a first round in which a cipher key is exclusively ORed with input data for the first round and a second round to receive an output from the first round, and the extracting comprises performing the extracting in the second round.

9. The method of claim 8 , wherein the second round comprises an inverse diffusion transformation.

10. The method of claim 7 , wherein processing the cipher text data and extracting the error correction data comprise performing the processing and extracting in a memory controller.

11. The method of claim 7 , wherein the plurality of successive rounds includes a final round, and wherein extracting error correction data further comprises extracting the error correction data prior to an InbSubBytes transformation in the final round.

12. An apparatus comprising:
a memory; and
a hardware memory controller to store encoded cipher text data in the memory, the hardware memory controller comprising:
an engine to process plain text data with an encryption cipher comprising a plurality of successive rounds having a final round and interleave error correction encoding within the encryption cipher prior to a stage of the final round associated with a linear substitution to generate the encoded cipher text data.

13. The apparatus of claim 12 , wherein the engine generates the encoded cipher text data in response to a write request associated with the plain text data.

14. The apparatus of claim 12 , wherein the engine, in response to a read request, decrypts and decodes the encoded cipher text data stored in the memory.

15. The apparatus of claim 12 , wherein the stage of the final round associated with the linear substitution is a SubBytes transformation stage.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Wang Han
• Foster Joseph E
• Venugopal Raghavan V
• Raymond Patrick A

Classifications

• H04L9/0631

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• H04L1/0042

  Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence) · CPC title

• H03M13/63 Primary

  Joint error correction and other techniques (H03M13/31 and H03M13/33 take precedence) · CPC title

• H04L2209/34

  Encoding or coding, e.g. Huffman coding or error correction · CPC title