Methods for fabricating anode shorted field stop insulated gate bipolar transistor

Patent metadata

Field	Value
Publication number	US-10050134-B2
Application number	US-201615177191-A
Country	US
Kind code	B2
Filing date	Jun 8, 2016
Priority date	Jul 27, 2011
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

First claim

What is claimed is:

1. A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT), comprising:
a) forming a semiconducting first epitaxial layer on a top surface of a semiconducting substrate, wherein the first epitaxial layer and substrate are of the same conductivity type and the first epitaxial layer has a lower concentration of charge carriers than the substrate;
b) forming a semiconducting field stop layer on top of the first epitaxial layer, wherein the field stop layer is of the same conductivity type as the substrate and first epitaxial layer, wherein the field stop layer has a higher concentration of charge carriers than the first epitaxial layer and a lower concentration of charge carriers than the substrate;
c) forming a semiconducting second epitaxial layer on top of the field stop layer, wherein the second epitaxial layer is of the same conductivity type as the substrate, first epitaxial layer, and field stop layer, wherein the second epitaxial layer has a lower concentration of charge carriers than that of the substrate and field stop layer;
d) forming one or more insulated gate bipolar transistors (IGBT) component cells in the second epitaxial layer;
e) thinning the substrate to a desired thickness by removing material from a back side of the substrate;
f) forming a metal pattern on a back surface of the substrate;
g) performing an anisotropic etch on the back side of the substrate using the metal pattern as a mask, wherein the anisotropic etch exposes one or more portions of the first epitaxial layer;
h) performing a backside blanket implant of dopants into the exposed portions of the first epitaxial layer to form implant regions, wherein the implant regions are of an opposite conductivity type to that of the substrate, first epitaxial layer, field stop layer, and second epitaxial layer; and
i) forming a metal layer on the back surface of the implant regions the metal pattern.

2. The method of claim 1 , wherein the substrate is doped n+ type, the first epitaxial layer is doped n− type, the field stop layer is doped is n type.

3. The method of claim 2 , wherein the second epitaxial layer is doped n− type.

4. The method of claim 2 , wherein the implant regions are doped p+ type.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Bhalla Anup
• Bobde Madhur
• Ding Yongping
• Zhang Xiaotian
• Ho Yueh-Se

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title