Bridge line structure for bit line connection in a three-dimensional semiconductor device

Patent metadata

Field	Value
Publication number	US-9613975-B2
Application number	US-201514675162-A
Country	US
Kind code	B2
Filing date	Mar 31, 2015
Priority date	Mar 31, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A structure is formed on a substrate, which includes a stack of alternating layers comprising insulating layers and electrically conductive layers and a plurality of memory stack structures extending through the stack. At least one bridge line structure is formed on top surfaces of a respective subset of the plurality of memory stack structures to provide local lateral electrical connection. At least one dielectric material layer is formed over the at least one bridge line structure and the plurality of memory stack structures. A plurality contact via structures is formed through the dielectric material layer. The plurality of contact via structures includes at least one first contact via structure contacting a top surface of a respective bridge line structure, and second contact via structures contacting a top surface of a respective memory stack structure.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device comprising:
a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;
a plurality of memory stack structures extending through the stack;
at least one bridge line structure contacting top surfaces of a respective subset of the plurality of memory stack structures;
an array of bit line structures overlying the at least one bridge line structure;
at least one first contact via structure contacting a respective bit line structure within the array of bit line structures and contacting a respective bridge line structure; and
second contact via structures contacting a respective bit line structure within the array of bit line structures and contacting a respective memory stack structure,

wherein the monolithic three-dimensional memory device has at least one feature selected from:
a first feature that each bottom surface of the at least one first contact via structure is located above a horizontal plane including top surfaces of the plurality of memory stack structures;
a second feature that a height of the second contact via structures is the same as a sum of a height of the at least one bridge line structure and a height of the at least one first contact via structure;
a third feature that each of the at least one first contact via structure and the at least one second contact via structure comprises a conductive metallic liner having a first metallic composition and a conductive fill material portion having a second metallic composition, and the at least one first contact via structure and the at least one second contact via structure are elongated along a lengthwise direction of the bit line structures within the array of bit line structures; or
a fourth feature that the monolithic three-dimensional memory device further comprises a backside contact via structure extending through the stack and contacting a portion of the substrate, wherein the at least one bridge line structure straddles the backside contact via structure without contacting the backside contact via structure.

2. The monolithic three-dimensional memory device of claim 1 , wherein each bottom surface of the at least one bridge line structure is coplanar with top surfaces of the plurality of memory stack structures.

3. The monolithic three-dimensional memory device of claim 1 , wherein the monolithic three-dimensional memory device has the first feature.

4. The monolithic three-dimensional memory device of claim 1 , wherein each bottom surface of the at least one first contact via structure is located above a horizontal plane including bottom surfaces of the second contact via structures.

5. The monolithic three-dimensional memory device of Claim 1 , wherein the monolithic three-dimensional memory device has the second feature.

6. The monolithic three-dimensional memory device of claim 1 , wherein the monolithic three-dimensional memory device has the third feature.

7. The monolithic three-dimensional memory device of claim 1 , wherein the monolithic three-dimensional memory device has the fourth feature.

8. The monolithic three-dimensional memory device of claim 7 , wherein:
a horizontal surface of a portion of the backside contact via structure that underlies the at least one bridge line structure is recessed below a horizontal plane including each bottom surface of the at least one bridge line structure; and
a topmost surface of the backside contact via structure is coplanar with the horizontal plane including each bottom surface of the at least one bridge line structure.

9. The monolithic three-dimensional memory device of claim 7 , wherein:
the at least one bridge line structure comprises a plurality of bridge line structures that laterally extend along a direction parallel to the array of bit line structures; and
one or more of the plurality of bridge line structures straddle the backside contact via structure.

10. The monolithic three-dimensional memory device of claim 7 , further comprising:
a source region comprising a doped semiconductor material, located within, or on, the substrate, and contacting a bottom surface of the backside contact via structure;
a plurality of vertical semiconductor channels located within the memory stack structures; and
a horizontal semiconductor channel contacting the source region and electrically shorted to the plurality of vertical semiconductor channels.

11. The monolithic three-dimensional memory device of claim 1 , wherein each memory stack structure within the plurality of memory stack structures has a greater lateral width along a horizontal direction that is perpendicular to a lengthwise direction of the array of bit line structures.

12. A monolithic three-dimensional memory device comprising:
a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;
a plurality of memory stack structures extending through the stack;
at least one bridge line structure contacting top surfaces of a respective subset of the plurality of memory stack structures;
an array of bit line structures overlying the at least one bridge line structure;
at least one first contact via structure contacting a respective bit line structure within the array of bit line structures and contacting a respective bridge line structure; and
second contact via structures contacting a respective bit line structure within the array of bit line structures and contacting a respective memory stack structure,

wherein:
each memory stack structure comprises a plurality of vertically stacked memory elements and a vertical semiconductor channel; and
each memory stack structure within the plurality of memory stack structures is electrically connected to a respective vertical semiconductor channel,
wherein:
each memory stack structure comprises, from outside to inside:
at least one blocking dielectric;
a memory material layer;
a tunneling dielectric; and
a respective vertical semiconductor channel;

the monolithic three-dimensional memory device further comprises an array of drain regions contacting a respective vertical semiconductor channel; and
a conductive element selected from a bit line structure and a second contact via structure contacts a top surface of a respective drain region within the array of drain regions.

13. A monolithic three-dimensional memory device comprising:
a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate;
a plurality of memory stack structures extending through the stack;
at least one bridge line structure contacting top surfaces of a respective subset of the plurality of memory stack structures;
an array of bit line structures overlying the at least one bridge line structure;
at least one first contact via structure contacting a respective bit line structure within the array of bit line structures and contacting a respective bridge line structure; and
second contact via structures contacting a respective bit line structure within the array of bit line structures and contacting a respective memory stack structure,

wherein:
the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Huang Chenche
• Wang Chun-Ming
• Mizutani Yuki
• Koketsu Hiroaki
• Hiroi Masayuki
• Higashitani Masaaki

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11551

  Electricity · mapped topic

• H01L27/11578 Primary

  Electricity · mapped topic