Semiconductor package having routable encapsulated conductive substrate and method

Patent metadata

Field	Value
Publication number	US-10049954-B2
Application number	US-201615173379-A
Country	US
Kind code	B2
Filing date	Jun 3, 2016
Priority date	Sep 8, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first laminated layer comprising:
a first surface finish layer;
first conductive patterns comprising first portions connected to the first surface finish layer and second portions laterally spaced apart from the first portions, wherein the second portions are devoid of the first surface finish layer;
conductive vias connected to the first portions of the first conductive patterns; and
a first resin layer covering the first conductive patterns, the conductive vias, and a portion of the first surface finish layer, wherein the first surface finish layer is exposed in a first surface of the first resin layer and the conductive vias are exposed in a second surface of the first resin layer, and wherein the conductive vias are substantially co-planar with the second surface of the first resin layer;

a second laminated layer adjacent the first laminated layer and comprising:
second conductive patterns connected to the conductive vias;
conductive pads connected to the second conductive patterns; and
a second resin layer covering at least a portion of the first resin layer, the second conductive patterns, and the conductive pads, wherein the conductive pads are exposed in a first surface of the second resin layer, and wherein the conductive pads exposed in the first surface of the second resin layer are recessed within openings in the second resin layer;

a semiconductor die electrically coupled to the first surface finish layer; and
an encapsulant covering at least a portion of the first laminated layer and the semiconductor die.

2. The semiconductor device of claim 1 , wherein:
surfaces of the conductive pads are recessed within openings in the second resin layer;
the semiconductor device further comprises conductive bumps connected to the conductive pads;
the semiconductor die comprises a first major surface, a second major surface opposite to the first major surface, and an outer perimeter surface extending between the first major surface and the second major surface;
at least one of the second portions of the first conductive patterns is disposed laterally outside of the outer perimeter of the semiconductor die; and
the second portions of the first conductive patterns are recessed within openings in the first resin layer.

3. The semiconductor device of claim 1 , wherein:
the first surface finish layer comprises one or more of nickel/gold (Ni/Au), silver (Ag) or copper (Cu); and
the first surface finish layer and the semiconductor die are electrically coupled by conductive wires.

4. The semiconductor device of claim 1 , wherein the conductive vias comprise copper and have a thickness in a range from approximately 20 microns through 100 microns.

5. The semiconductor device of claim 1 , wherein the first laminated layer, the second laminated layer, and the encapsulant have edge surfaces that are substantially co-planar.

6. The semiconductor device of claim 1 , wherein:
the first portions of the first conductive patterns are wider than the second portions of the first conductive patterns in a cross-sectional view;
the semiconductor die laterally overlaps at least part of the second portions of the first conductive patterns and laterally overlaps portions of the first surface finish layer in the cross-sectional view;
the first resin layer, the second resin layer, and the encapsulant comprise a mold compound material; and
the first seed layer completely covers the first portions of the first conductive patterns such that the first portions are not exposed in the first resin layer.

7. The semiconductor device of claim 1 , wherein:
the first portions of the first conductive patterns are wider than the conductive vias in a cross-sectional view;
portions of the second conductive patterns are provided absent the conductive pads; and
the first resin layer, the second resin layer, and the encapsulant comprise mold compound materials having similar thermal coefficients of expansion.

8. The semiconductor device of claim 1 , wherein:
the first surface finish layer is substantially coplanar with the first resin layer; and
surfaces of the second portions of the first conductive patterns are recessed below the first surface of the first resin layer.

9. A semiconductor device comprising:
a first laminated layer comprising:
a first surface finish layer;
first conductive patterns comprising first portions connected to the first surface finish layer and second portions laterally spaced apart from the first portions, wherein the second portions are devoid of the first surface finish layer;
conductive vias connected to the first portions of the first conductive patterns but not physically connected to the second portions of the first conductive patterns; and
a first resin layer covering the first conductive patterns, the conductive vias, and a portion of the first surface finish layer, wherein the first surface finish layer is exposed in a first surface of the first resin layer, and wherein the conductive vias are exposed in a second surface of the first resin layer, and wherein the conductive vias are substantially co-planar with the second surface of the first resin layer, and wherein the second portions of the first conductive patterns are recessed within first openings in the first resin layer;

a second laminated layer adjacent the first laminated layer and comprising:
second conductive patterns connected to the conductive vias;
conductive pads connected to at least a portion of the second conductive patterns; and
a second resin layer covering at least a portion of the first resin layer, the second conductive patterns, and the conductive pads, wherein the conductive pads are exposed in a first surface of the second resin layer, and wherein the conductive pads are recessed within second openings in the second resin layer;

a semiconductor die electrically coupled to the first surface finish layer; and
an encapsulant covering at least a portion of the first laminated layer and the semiconductor die.

10. The semiconductor device of claim 9 , wherein:
the semiconductor device further comprises conductive bumps connected to the conductive pads;
portions of the conductive bumps laterally overlap onto the first surface of the second resin layer;
the semiconductor die comprises a first major surface, a second major surface opposite to the first major surface, and an outer perimeter surface extending between the first major surface and the second major surface; and
at least one of the second portions of the first conductive patterns is disposed laterally outside of the outer perimeter of the semiconductor die.

11. The semiconductor device of claim 9 , wherein:
the first surface finish layer comprises one or more of nickel/gold (Ni/Au), silver (Ag) or copper (Cu);
a major surface of the semiconductor die is attached to the first laminated layer with an adhesive layer;
the adhesive layer is interposed between the major surface of the semiconductor die and overlaps parts of the first portion of the first conductive patterns and overlaps parts of the second portion of the first conductive patterns; and
the first surface finish layer and the semiconductor die are electrically coupled by conductive wires.

12. The semiconductor device of claim 9 , wherein:
the semiconductor die laterally overlaps part of the second portions of the first conductive patterns and portions of the first surface finish layer in a cross-sectional view;
the second portions of the first conductive patterns are provided absent the first surface finish layer;
the first resin layer, the second resin layer, and the

Assignees

• Amkor Technology Inc
• Amkor Technology Inc

Inventors

• Bang Won Bae
• Kim Byong Jin
• Kim Gi Jeong
• Kwon Jae Doo
• Jeon Hyung Il

Classifications

• H10W70/6565

  recessed into the surface of the package substrates, interposers, or redistribution layers · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title