Flushing control within a multi-threaded processor

Patent metadata

Field	Value
Publication number	US-10049043-B2
Application number	US-201615152775-A
Country	US
Kind code	B2
Filing date	May 12, 2016
Priority date	Jun 2, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A data processing apparatus 2 performs multi-threaded processing using the processing pipeline 6, 8, 10, 12, 14, 16, 18. Flush control circuitry 30 is responsive to multiple different types of flush trigger. Different types of flush trigger result in different sets of state being flushed for the thread which resulted in the flush trigger with state for other thread not being flushed. For example, a relatively low latency stall may result in flushing back to a first flush point whereas a longer latency stall results in flushing back to a second flush point and the loss of more state data. The data flushed back to the first flushed point may be a subset of the data flushed back to the second flush point.

First claim

I claim:

1. Apparatus for processing data comprising:
processing circuitry to execute in parallel processing operations corresponding to a plurality of threads of processing operations; and
flush control circuitry responsive to detection of a flush trigger for a given processing thread among said plurality of threads to control flushing of state for said given thread from said processing circuitry; and
a hierarchical memory having a plurality of memory levels,

wherein:
a first type of flush trigger corresponds to an access to a first memory level within said plurality of memory levels;
a second type of flush trigger corresponds to an access to a second memory level within said plurality of memory levels and different from said first memory level;
when said flush trigger is said first type of flush trigger, said state is a first set of state; and
when said flush trigger is said second type of flush trigger, said state is a second set of state different from said first set of state.

2. Apparatus as claimed in claim 1 , wherein said first set of state is a proper subset of said second set of state.

3. Apparatus as claimed in claim 1 , wherein said flushing of state for said given processing thread permits said processing circuitry to process additional processing operations of one or more other threads among said plurality of thread and different from said given thread.

4. Apparatus as claimed in claim 1 , wherein said hierarchical memory comprises first level cache memory, second level cache memory and further memory, said first type of flush trigger corresponds to a miss within said first level cache memory resulting in an access to said second level of cache memory and said second type of flush trigger corresponds to a miss within said second level cache memory resulting in an access to said further memory.

5. Apparatus as claimed in claim 1 , wherein said first level memory has a first access latency, said second level memory has a second access latency, said first access latency being less than said second access latency.

6. Apparatus as claimed in claim 1 , wherein said processing circuitry comprises first instruction storage circuitry to store first instruction data for said given thread and second instruction storage circuitry to store second instruction data for said given thread and corresponding to first instruction data for said given thread read from said first instruction storage circuitry, said second set of state includes said second instruction data and said first set of state excludes said second instruction data.

7. Apparatus as claimed in claim 6 , wherein said first instruction storage circuitry comprises an instruction cache.

8. Apparatus as claimed in claim 6 , wherein said second instruction storage circuitry comprises instruction queue circuitry to store instruction data fetched following program flow within said plurality of threads.

9. Apparatus as claimed in claim 8 , wherein said second type of flush trigger for said given thread triggers flushing of instruction data for said given thread from said instruction queue and said first type of flush trigger for said given thread triggers leaves instruction data for said given thread stored in said instruction queue.

10. Apparatus as claimed in claim 6 , comprising branch prediction circuitry to predict program flow within said plurality of treads and wherein said second instruction data is stored in said second instruction storage in dependence upon branch prediction operations performed by said branch prediction circuitry.

11. Apparatus as claimed in claim 6 , wherein comprising instruction pre-processing circuitry to perform one or more pre-processing operations upon said first instruction data read from said first instruction storage circuitry to form said second instruction data to be stored within said second instruction storage circuitry.

12. Apparatus as claimed in claim 1 , wherein said processing circuitry comprises at least one execution pipeline, said first set of state and said second set of state both including pipeline state data corresponding to partial execution of processing operations of said given thread by said one or more processing pipelines.

13. Apparatus as claimed claim 1 , wherein said processing circuitry is out-of-order processing circuitry to control execution of processing operations in an order other than following a program flow order and said flushing of state corresponding to state in respect of processing operations following a given flush triggering instruction within said program flow order with instructions preceding said given flushing triggering instruction within said program flow order permitted to complete.

14. Apparatus as claimed in claim 1 , wherein said processing circuitry is in-order processing circuitry to control execution of processing operations in an order following a program flow order and said flushing of state corresponding to state in respect of processing operations following a given flush triggering instruction within said program flow order with instructions preceding said given flushing triggering instruction within said program flow order permitted to complete.

15. Apparatus as claimed in claim 1 , wherein said first type of flush trigger corresponds to detection of execution of a long-latency processing operation associated with a long execution latency.

16. Apparatus as claimed in claim 15 , wherein said long-latency processing operation is one of:
an operation processed by an accelerator;
an operation processed by a co-processor;
a system instruction; and
a long latency instruction.

17. Apparatus for processing data, comprising:
processing means for executing in parallel processing operations corresponding to a plurality of threads of processing operations; and
flush control means, responsive to detection of a flush trigger for a given processing thread among said plurality of threads, for controlling flushing of state for said given thread from said processing circuitry; and
a hierarchical memory means having a plurality of memory levels,

wherein:
a first type of flush trigger corresponds to an access to a first memory level within said plurality of memory levels;
a second type of flush trigger corresponds to an access to a second memory level within said plurality of memory levels and different from said first memory level;
when said flush trigger is said first type of flush trigger, said state is a first set of state; and
when said flush trigger is said second type of flush trigger, said state is a second set of state different from said first set of state.

18. A method of processing data comprising:
executing in parallel processing operations corresponding to a plurality of threads of processing operations; and
in response to detection of a flush trigger for a given processing thread among said plurality of threads, controlling flushing of state for said given thread from said processing circuitry,

wherein:
a first type of flush trigger corresponds to an access to a first memory level within a plurality of memory levels of a hierarchical memory;
a second type of flush trigger corresponds to an access to a second memory level within said plurality of memory levels and different from said first memory level;
when said flush trigger is said first type of flush trigger, said state is a first set of state; and
when said flush trigger is said second type of flush trigger, said state is a second set of state different from said first set of state.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Greenhalgh Peter Richard

Classifications

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title