Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands

Patent metadata

Field	Value
Publication number	US-10049006-B2
Application number	US-201514963035-A
Country	US
Kind code	B2
Filing date	Dec 8, 2015
Priority date	Dec 8, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer; and c) during the refresh, performing an ERR Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array.

First claim

What is claimed is:

1. A method for updating a DRAM memory array, said method comprising:
a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller;
b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data using an associated sense amplifier buffer;
c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array, wherein the ECC scrub operation comprises performing a virtual read and write operation, wherein the selected bits are identified using a refresh column counter; and
d) updating the refresh column counter.

2. The method of claim 1 , wherein the updating comprises:
d) updating the refresh column counter to set the refresh column counter to select a different set of bits from the selected bits of the activated row of the DRAM memory array for applying a subsequent ECC scrub operation to the different set of bits.

3. The method of claim 2 , further comprising:
repeating the c) and d) to select and perform an ECC scrub of subsequent bits in the activated row.

4. The method of claim 3 , further comprising:
repeating the b), c) and d) for subsequent refresh operations to perform an ECC scrub over all columns for all rows of the DRAM memory array.

5. The method of claim 2 , wherein the virtual read and write operation is operable to re-circulate selected data bits through an ECC repair module and store corrected data from the ECC repair module back in the sense amplifier buffer.

6. The method of claim 2 , further comprising:
activating another row of data using the associated sense amplifier buffer; and
performing an ECC scrub operation for bits over the another row in the DRAM memory array during subsequent memory controller initiated transitions to the refresh state.

7. The method of claim 1 , wherein the refresh state is part of an all bank refresh operation.

8. The method of claim 4 , further comprising:
incrementing a bank counter to address a different portion of the DRAM memory array.

9. The method of claim 1 , wherein the refresh state is part of a per bank refresh operation.

10. The method of claim 1 , wherein the performing an ECC scrub further comprises:
reading in the selected bits and corresponding ECC bits;
determining if the selected bits are correct using the corresponding ECC bits;
correcting the selected bits if the determining indicates an error;
re-computing the ECC bits for the selected bits; and
writing corrected data and ECC bits back into the sense amplifier buffer of the DRAM memory array.

11. The method of claim 10 , wherein an address associated with bits of any detected error is stored in a temporary buffer or register.

12. A method for updating a DRAM memory array, said method comprising:
a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller;
b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a plurality of rows of data using associated sense amplifier buffers;
c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in the plurality of activated rows of the DRAM memory array, wherein the ECC scrub operation comprises performing a virtual read and write operation and the selected bits are identified using a refresh column counter; and
d) updating the refresh column counter.

13. The method of claim 12 , wherein the updating the refresh column counter comprises:
setting the refresh column counter to select a different set of bits from the selected bits of the plurality of activated rows of the DRAM memory array for applying a subsequent ECC scrub operation.

14. The method of claim 13 , further comprising:
repeating the c) and d) to select and perform an ECC scrub of subsequent bits in the plurality of activated rows.

15. The method of claim 14 , further comprising:
repeating the b), c) and d) for subsequent refresh operations to perform an ECC scrub over all columns for all rows of the DRAM memory array.

16. The method of claim 13 , wherein the virtual read and write operation is operable to re-circulate selected data bits through associated ECC repair modules and store corrected data from the associated ECC repair modules back in the associated sense amplifier buffers.

17. The method of claim 12 , wherein the refresh state is part of an all bank refresh operation.

18. The method of claim 12 , wherein the refresh state is part of a per bank refresh operation.

19. The method of claim 15 , further comprising:
incrementing a bank counter to address a different portion of the DRAM memory array.

20. The method of claim 12 , wherein the performing an ECC scrub further comprises:
reading in the selected bits and corresponding ECC bits;
determining the selected bits are correct using the corresponding ECC bits;
correcting the selected bits if the determining indicates an error;
re-computing the ECC bits for the selected bits; and
writing corrected data and ECC bits back into the sense amplifier buffer of the DRAM memory array.

21. An apparatus for updating a DRAM memory array, said apparatus comprising:
the DRAM memory array, wherein the DRAM memory array is configured to:
a) transition the DRAM memory array to a refresh state from an idle state in accordance with a command from a memory controller;
b) initiate a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data using an associated sense amplifier buffer;
c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array wherein the ECC scrub operation comprises performing a virtual read and write operation and the selected bits are identified using a refresh column counter; and
d) updating the refresh column counter to select a different set of bits from the selected bits of the plurality of activated rows of the DRAM memory array for applying a subsequent ECC scrub operation to the different set of bits.

22. The method of claim 21 , wherein the ECC scrub operation further comprises:
reading the selected bits and ECC bits that correspond to the selected bits;
determining, using the ECC bits, if the selected bits include an error;
correcting the selected bits if the selected bits are determined to include an error and;
writing the corrected selected bits and ECC bits back to the DRAM memory array.

Assignees

• Nvidia Corp

Inventors

• Reed David
• Gupta Alok

Classifications

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C29/04 Primary

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title