Controlling power consumption

Patent metadata

Field	Value
Publication number	US-10048740-B2
Application number	US-201514814903-A
Country	US
Kind code	B2
Filing date	Jul 31, 2015
Priority date	Jul 31, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A computing system comprises one or more multicore processor(s) comprising a set of multiple processing units each operable at a variable frequency, and a main memory operable at a variable frequency. A feedback controller is configured to control the frequency of each processing unit of the set and the frequency of the main memory dependent on a measure representative of a current performance of an application running on one or more of the multiple processing units of the set.

First claim

What is claimed is:

1. A computing system comprising:
one or more multicore processors, wherein each multicore processor comprises a set of one or more processing units, wherein each processing unit is operable at a variable frequency;
a main memory, wherein the main memory is operable at a variable frequency; and
a feedback controller, wherein the feedback controller is configured to control the variable frequency of a processing unit of the set of one or more processing units,
wherein the feedback controller is configured to operate a first predictive model of performance measurement for a first application by determining a first application specific performance measurement dependent on
a sum of weighted linear frequencies of a first subset of the one or more processing units which the first application is supposed to run on, and a weighted linear frequency of the main memory,
wherein the feedback controller is configured to control the variable frequency of each processing unit of the first subset and control the frequency of the main memory, wherein the feedback controller determines the frequency of each said processing unit of the first subset and the main memory from a minimized value of a weighted sum of power consumption of the first subset and a first performance degradation of the first application,
wherein the first performance degradation of the first application is defined as a deviation of the first application specific performance measurement from the first predictive model of performance measurement.

2. The computing system according to claim 1 , wherein the feedback controller is configured to control the variable frequency of each processing unit of the set of processing units, and the variable frequency of the main memory is dependent on the determined measurement.

3. The computing system according to claim 1 , further comprising a power supply providing power to at least one of the one or more multicore processors and to the main memory,
wherein the feedback controller is configured to control the variable frequency of each processing unit of the set of one or more processing units and the variable frequency of the main memory, in addition the feedback controller is dependent on a measurement representative of a current power supplied by the power supply.

4. The computing system according to claim 1 , wherein the feedback controller is configured to operate a predictive model of power consumption by determining a consumed power, the consumed power is dependent on the variable frequencies of each processing unit of the set of one or more processing units and the variable frequency of the main memory.

5. The computing system according to claim 4 , wherein in the predictive model of power consumption, the consumed power is determined by adding weighted linear frequencies of the processing units of the set of one or more processing units and a weighted linear frequency of the main memory.

6. The computing system according to claim 1 , wherein the feedback controller is configured to operate a predictive model of performance measurement for each application by determining an application specific performance measurement dependent on the frequencies of the processing units of the set of one or more processing units the application is supposed to run on and dependent on the frequency of the main memory.

7. The computing system according to claim 1 , wherein the feedback controller is configured to determine the frequency of each processing unit of the set of one or more processing units by which said processing unit is to be controlled in a next step and the frequency of the main memory by which the main memory is to be controlled in a next step by respecting at least one target of performance measurement provided for each application.

8. The computing system according to claim 1 , wherein the feedback controller includes a Model Predictive Controller.

9. The computing system according to claim 1 ,
wherein the feedback controller is configured to operate a set of predictive models of performance measurements for corresponding set of applications by determining a set of predictive application specific performance measurements dependent on a sum of weighted linear frequencies of a corresponding subset of one or more processing units the corresponding application is supposed to run on, and a weighted linear frequency of the main memory,
wherein the feedback controller is configured to control the variable frequency of each processing unit of the set of one or more processing units and control the frequency of the main memory by minimizing a weighted sum of power consumption of the of each processing unit of the set of one or more processing units and a set of performance degradations corresponding to the set of applications.

10. A method for operating a computing system comprising:
one or more multicore processors with a set of multiple processing units each operable at a variable frequency, comprising a main memory operable at a variable frequency, and comprising a power supply providing power at least to the one or more multicore processor and to the main memory, the method comprising:
providing a predictive model of performance measurement of a current performance of a respective application, for each application of a set of applications co-running on the set of multiple processing units, wherein the measurement is dependent on a sum of weighted linear frequencies of a correspond subset of the multiple processing units which the corresponding application is supposed to run on, and a weighted linear frequency of the main memory;
providing a power measurement representative of a current power supplied by the power supply; and
controlling via a feedback controller, the frequency of each processing unit of the set of multiple processing units and the frequency of the main memory, wherein the feedback controller determines the frequency of each said processing unit of the set of multiple processing units and the frequency of the main memory from a set of deviations between a weighted sum of the predictive models of performance measurements of each application of the set of applications co-running and the power measurement.

11. The method according to claim 10 , comprising:
operating a predictive model of power consumption by determining a consumed power dependent on the frequencies of each said processing unit and dependent on the frequency of the main memory; and
operating a predictive model of performance measurement for each application of the set of applications co-running by determining an application specific predictive model of performance measurement dependent on the frequencies of the processing units the application is supposed to run on and the frequency of the main memory.

12. The method according to claim 11 , comprising:
determining the frequency to control each processing unit of the set of multiple processing units within a next step and determining the frequency to control the main memory within a next step by minimizing a weighted sum of power consumption and performance degradation per application of a set of applications co-running wherein the performance degradation per application is defined as a deviation of the performance measurement from the predictive model of performance measurement.

13. The method according to claim 10 , wherein determining the frequency for each processing unit of the set of multiple processing units and the frequency of the main memory is calculated by applying a Model Predictive Controller.

14. A computer program product for operating a computing system, the computer progra

Assignees

• IBM

Inventors

• Birke Robert
• Chen Yiyu L
• Engbersen Antonius P
• Schmatz Martin L
• Wang Cheng

Classifications

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02D10/126

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title