Tracking pipelined activity during off-core memory accesses to evaluate the impact of processor core frequency changes

Patent metadata

Field	Value
Publication number	US-9600392-B2
Application number	US-201414456198-A
Country	US
Kind code	B2
Filing date	Aug 11, 2014
Priority date	Aug 11, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.

First claim

What is claimed is:

1. A system for tracking pipelined activity during off-core memory accesses, comprising:
at least one processor core comprising at least one execution unit;
at least one counter operative to track a number of cycles in which the at least one execution unit of the at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising a plurality of cycles, the at least one counter operative to track the number of cycles on at least one multi-cycle execution unit from among the at least one execution unit that requires more than one cycle to complete execution of at least one operation; and
a controller for evaluating an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions tracked in the at least one counter during the interval.

2. The system according to claim 1 , wherein the at least one counter operative to track a number of cycles in which the at least one execution unit of the at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising a plurality of cycles further comprises:
a first counter of the at least one counter operative to track each cycle of the plurality of cycles during which none of the at least one execution unit is finishing execution and the at least one thread of the at least one processor core is waiting on at least one off-core memory access; and
a second counter of the at least one counter operative to track each cycle of the plurality of cycles during which none of the at least one execution unit is busy and the at least one thread of the at least one processor core is waiting on at least one off-core memory access.

3. The system according to claim 2 , further comprising:
the controller operative to evaluate the value in the first counter as a measure for an upper bound on a first number of cycles that can be reduced by a frequency change comprising a slower frequency that will not impact performance as measured by a pipeline throughput of the at least one processor core; and
the controller operative to evaluate the value in the second counter as a measure for a lower bound on a second number of cycles that can be reduced by a frequency change comprising a slower frequency that will not impact the performance as measured by the pipeline throughput of the at least one processor core.

4. The system according to claim 2 , further comprising:
the second counter operative to track, during a first interval running at a first frequency, each cycle of the plurality of cycles of a workload during which none of the at least one execution unit is busy and the at least one thread of the at least one processor core is waiting on at least one off-core memory access, as a first counter value;
the controller operative to store the first counter value;
the second counter operative to track, during a second interval running at a second frequency, each cycle of the plurality of cycles of the workload during which none of the at least one execution unit is busy and the at least one thread of the at least one processor core is waiting on at least one off-core memory access, as a second counter value, wherein the second frequency is slower than the first frequency;
the controller operative to calculate a separate ratio for each interval, wherein the separate ratio comprises a value in the second counter for the interval over a frequency for the interval; and
the controller operative to determine a change in frequency sensitivity from the first frequency to the second frequency from a difference between a first ratio calculated for the first frequency and a second ratio calculated for the second frequency, wherein the change in frequency sensitivity provides an indicator of the expected performance impact of an additional frequency change within the at least one processor core.

5. The system according to claim 1 , wherein the at least one counter operative to track a number of cycles in which the at least one execution unit of the at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising a plurality of cycles further comprises:
the at least one counter operative to track the number of cycles on at least one multi-cycle execution unit from among the at least one execution unit that requires more than one cycle to complete execution of at least one operation and on at least one single cycle execution unit from among the at least one execution unit that requires one cycle to complete execution of the at least one operation.

6. A computer program product for tracking pipelined activity during off-core memory accesses, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
track, by the processor, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core of the processor is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising a plurality of cycles, the at least one counter operative to track the number of cycles on at least one multi-cycle execution unit from among the at least one execution unit that requires more than one cycle to complete execution of at least one operation; and
evaluate, by the processor, an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions tracked in the at least one counter during the interval.

7. The computer program product according to claim 6 , further comprising the program instructions executable by the processor to cause the processor to:
track, by the processor, in a first counter of the at least one counter, each cycle of the plurality of cycles during which none of the at least one execution unit is finishing execution and the at least one thread of the at least one processor core is waiting on at least one off-core memory access; and
track, by the processor, in a second counter of the at least one counter, each cycle of the plurality of cycles during which none of the at least one execution unit is busy and the at least one thread of the at least one processor core is waiting on at least one off-core memory access.

8. The computer program product according to claim 7 , further comprising the program instructions executable by the processor to cause the processor to:
evaluate, by the processor, the value in the first counter as a measure for an upper bound on a first number of cycles that can be reduced by a frequency change comprising a slower frequency that will not impact performance as measured by a pipeline throughput of the at least one processor core; and
evaluate, by the processor, the value in the second counter as a measure for a lower bound on a second number of cycles that can be reduced by a frequency change comprising a slower frequency that will not impact the performance as measured by the pipeline throughput of the at least one processor core.

9. The computer program product according to claim 7 , further comprising the program instructions executable by the processor to cause the processor t

Assignees

• IBM

Inventors

• Hanson Heather L
• Indukuru Venkat R
• O'Connell Francis P
• Rajamani Karthick

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F11/3466 Primary

  Performance evaluation by tracing or monitoring · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic