Electronic device package having a dielectric layer and an encapsulant

Patent metadata

Field	Value
Publication number	US-10043782-B2
Application number	US-201715470960-A
Country	US
Kind code	B2
Filing date	Mar 28, 2017
Priority date	Apr 4, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A method for fabricating an electronic device package includes providing a carrier, disposing a semiconductor chip onto the carrier, the semiconductor chip having a contact pad on a main face thereof remote from the carrier, applying a contact element onto the contact pad, applying a dielectric layer on the carrier, the semiconductor chip, and the contact element, and applying an encapsulant onto the dielectric layer.

First claim

What is claimed is:

1. A method for fabricating an electronic device package, the method comprising:
providing a carrier;
disposing a semiconductor chip onto the carrier, the semiconductor chip comprising a contact pad on a main face of the semiconductor chip;
applying a contact element onto the contact pad;
applying a dielectric layer on the carrier, the semiconductor chip, and the contact element; and
applying an encapsulant onto the dielectric layer.

2. The method of claim 1 , wherein the dielectric layer comprises one or more of a polymer layer, polyimide layer, a parylene layer, a polybenzoxazole layer, an epoxy resin layer, a silicone layer, a spin-on glass layer, a semiconductor oxide layer, a semiconductor nitride layer and a semiconductor oxynitride layer.

3. The method of claim 1 , wherein the dielectric layer comprises one or more of the following properties:
a dielectric constant in a range from 2 to 5;
a dielectric strength in a range from 100 V/μm to 500 V/μm;
a dissipation factor in a range from 0.005 to 0.03; and
a modulus of elasticity in a range from 0.1 to 5.0 GPa.

4. The method of claim 1 , wherein the dielectric layer is applied with a thickness in a range from 2 μm to 100 μm.

5. The method of claim 1 , wherein applying the dielectric layer comprises one or more of:
spin coating;
spray coating;
jet coating;
electrostatic coating and/or atomizing coating or ion atomizing;
wave coating;
potting;
filling;
laminating;
dipping;
physical vapor deposition;
chemical vapor deposition; and
printing.

6. The method of claim 1 , further comprising:
heating or curing the deposited dielectric layer at a heating temperature in a range up to 500° C. and a heating time in a range up to 5 h.

7. The method of claim 1 , wherein applying the dielectric layer comprises:
applying a stack of two or more dielectric layers of one or more of different materials or of different properties.

8. The method of 1 , wherein applying the dielectric layer comprises:
depositing a first dielectric layer and treating the deposited first dielectric layer with a first set of conditions; and
depositing a second dielectric layer and treating the deposited second dielectric layer with a second set of conditions different from the first set of conditions.

9. The method of claim 8 , wherein the first set of conditions comprises a first heating temperature and a first heating time, and wherein the second set of conditions comprises a second heating temperature and a second heating time.

10. The method of claim 1 , wherein applying the encapsulant comprises:
applying a host material comprising one or more of a resin, an epoxy silicone, an epoxy polyimide, a bismaleimide, a cyanate ester, and a thermoplast.

11. The method of claim 1 , wherein applying the encapsulant comprises:
applying a host material comprising filler increments embedded therein, the filler increments being made of SiO, Al2O3, ZnO, MgO, AlN, Si3N4, BN, a ceramic material, or a metallic material.

12. The method of claim 1 , wherein the encapsulant is applied by transfer molding, compression molding, vacuum casting, or laminating.

Assignees

• Infineon Technologies Ag

Inventors

• Fuergut Edward
• Doepke Holger
• Hohlfeld Olaf
• Juerss Michael

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5434

  the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires · CPC title