Molded chip package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9780061-B2
Application number	US-201414287080-A
Country	US
Kind code	B2
Filing date	May 26, 2014
Priority date	May 26, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A method of manufacturing a molded chip package is provided which comprises arranging an electronic chip on a supporting structure; forming an isolation layer at least on portions of the electronic chip; and molding an encapsulation which covers the electronic chip and the supporting structure at least partially by using a molding material comprising a matrix material and a conductive filler material.

First claim

What is claimed is:

1. A molded chip package, comprising:
an electronic chip arranged on a support structure and comprising a front side and a back side, wherein at least two electronic contacts are formed on the electronic chip, wherein a first one of the at least one electronic contacts is formed on the front side and a second one of the electronic contacts is formed on the back side;
a selective isolation layer arranged on one of the electronic contacts such that the electronic contact on the back side is only partially covered by the selective isolation layer;

wherein the selective isolation layer is formed on portions of the support structure,
wherein the selective isolation layer is formed on side walls of the electronic chip between the front side and the back side, and
a molded encapsulation covering at least the back side of the electronic chip together with the second one of the electronic contacts and side walls of the electronic chip, wherein the molded encapsulation comprises a matrix material and a conductive filler material, such that the encapsulation is useable as a contacting layer for the electronic contact on the back side for forming an electrically conducting path for the contact on the back side.

2. The molded chip package according to claim 1 , wherein the conductive filler material is a heat conductive material having a coefficient of heat conductivity of more than 70 W/mK.

3. The molded chip package according to claim 1 , wherein the conductive filler material is an electrically conductive material having a specific electric conductivity of more than 1010 6 S/m.

4. The molded chip package according to claim 1 , further comprising a redistribution layer electrically connected to at least one of the electronic contacts.

5. The molded chip package according to claim 1 , wherein the isolation layer comprises as isolating material at least one material selected out of the group consisting of:
parylene;
amide;
passivation materials; and
oxides.

6. The molded chip package according to claim 1 , wherein the support structure is a lead frame.

7. The molded chip package according to claim 6 , wherein the first contact is electrically connected to the lead frame by an electrically conductive structure, wherein the selective insulation is formed on the electrically conductive structure.

8. The molded chip package according to claim 6 , wherein the isolation layer covers portions of the lead frame.

9. The molded chip package according to claim 1 , wherein the isolation layer has a thickness of less than 100 micrometer.

10. The molded chip package according to claim 1 , comprising a plurality of electronic chips.

11. A method of manufacturing a molded chip package, the method comprising:
arranging an electronic chip on a support structure, comprising a front side and a back side, wherein at least two electronic contacts are formed on the electronic chip, wherein a first one of the at least one electronic contacts is formed on the front side and a second one of the electronic contacts is formed on the back side;
forming an isolation layer at least on portions of the electronic chip;
arranging the isolation layer on one of the electronic contacts such that the electronic contact on the back side is only partially covered by the isolation layer;
forming the isolation layer on portions of the support structure,
forming the isolation layer on side walls of the electronic chip between the front side and the back side; and
molding an encapsulation which covers at least the back side of the electronic chip together with the second one of the electronic contacts and side walls of the electronic chip and the support structure at least partially by using a molding material comprising a matrix material and a conductive filler material, such that the encapsulation is useable as a contacting layer for the electronic contact on the back side for forming an electrically conducting path for the contact on the back side.

12. The method according to claim 11 , wherein a plurality of electronic chips is arranged on the supporting structure before the encapsulation is molded and the method further comprising:
singulizing the electronic chips after the encapsulation is molded.

13. The method according to claim 11 , wherein the molding is performed by one of the processes of the group of processes consisting of:
compression molding;
transfer molding; and
injection molding.

14. The method according to claim 11 , wherein the supporting structure is a temporary carrier and wherein the method further comprises:
removing the supporting structure after molding the encapsulation; and
forming a redistribution layer contacting at least one contact of the electronic chip.

15. A method of manufacturing a molded chip package, the method comprising:
providing a leadframe comprising at least one chip reception area;
arranging an electronic chip having at least one contact pad on a front side of the electronic chip onto the chip reception area, and comprising a back side, wherein at least one electronic contact is formed on the back side;
connecting the at least one contact pad to a portion of the leadframe by an electrically conductive structure;
selectively forming an isolation layer on the electrically conductive structure;
arranging the isolation layer on one of the electronic contacts such that the electronic contact on the back side is only partially covered by the isolation layer;
forming the isolation layer on portions of the leadframe,
forming the isolation layer on side walls of the electronic chip between the front side and the back side; and
molding an encapsulation covering at least the electrically conductive structure and covering at least the back side of the electronic chip together with a second one of the electronic contacts and side walls of the electronic chip by using a molding material comprising a matrix material and a conductive filler material, such that the encapsulation is useable as a contacting layer for the electronic contact on the back side for forming an electrically conducting path for the contact on the back side.

16. The method according to claim 15 , wherein the isolation layer has a thickness of less than 15 micrometer.

17. The method according to claim 15 , wherein the isolation layer is formed by a chemical vapor deposition process.

18. The method according to claim 15 , wherein the conductive filler material is formed by metal particles.

19. The method according to claim 15 , wherein the matrix material is a material selected out of the group consisting of:
thermoset material;
thermoplast material.

20. The method according to claim 16 , wherein the filler material may constitute between 10 vol % and 95 vol % of the molding material.

Assignees

• Infineon Technologies Ag

Inventors

• Gabler Franz
• Theuss Horst

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title