Semiconductor package structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10043757-B2
Application number	US-201514708249-A
Country	US
Kind code	B2
Filing date	May 10, 2015
Priority date	Sep 17, 2014
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a package body having opposing first and second surfaces;
a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body;
a semiconductor component embedded in the package body and disposed on and electrically connected to the first conductive pads; and
a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body.

2. The semiconductor package structure of claim 1 , further comprising a stack member disposed on the first surface of the package body and electrically connected to the first conductive pads and the second conductive pads.

3. The semiconductor package structure of claim 2 , wherein the stack member comprises:
an electronic component disposed on the first surface of the package body and electrically connected to the first conductive pads and the second connecting pads; and
an encapsulant formed on the first surface of the package body, for encapsulating the electronic component.

4. The semiconductor package structure of claim 2 , wherein the electronic component is a substrate, a semiconductor chip, an interposer, or a packaged or unpackaged semiconductor component.

5. The semiconductor package structure of claim 1 , wherein the semiconductor component is an active component or a passive component.

6. The semiconductor package structure of claim 1 , further comprising an insulating layer formed on the second surface of the package body and having a plurality of first openings, from which the second ends of the conductive elements are exposed.

7. The semiconductor package structure of claim 1 , further comprising a plurality of solder pads formed on the second ends of the conductive elements.

8. The semiconductor package structure of claim 7 , wherein each of the solder pads comprises a conductive layer formed on the second end of a corresponding one of the conductive elements and a metal layer formed on the conductive layer.

9. The semiconductor package structure of claim 7 , further comprising a surface finish layer formed on exposed surfaces of the solder pads, the first conductive pads and the second conductive pads.

10. The semiconductor package structure of claim 1 , wherein the package body is made of a molding compound, a prepreg, or a photosensitive dielectric material.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Pai Yu-Cheng
• Hsiao Wei-Chung
• Chiu Shih-Chao
• Lin Chun-Hsien
• Sun Ming-Chen
• Shen Tzu-Chieh
• Chen Chia-Cheng

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title