Semiconductor package devices integrated with inductor

Patent metadata

Field	Value
Publication number	US-10043745-B2
Application number	US-201615088128-A
Country	US
Kind code	B2
Filing date	Apr 1, 2016
Priority date	Apr 1, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

The present disclosure provides an inductor structure. The inductor structure, comprising a first surface, a second surface intersecting with the first surface, a first conductive pattern and a second conductive pattern. The first conductive pattern is formed on the first surface. The second conductive pattern is formed on the second surface. The first conductive pattern is connected with the second conductive pattern.

First claim

What is claimed is:

1. An inductor structure, comprising:
a first surface and a second surface intersecting with the first surface;
a first conductive pattern on the first surface, comprising a plurality of first conductive metals;
a second conductive pattern on the second surface, comprising:
a plurality of conductive contacts, each in direct contact with one of the plurality of the first conductive metals on the first surface; and
a plurality of second conductive metals, each perpendicular to one of the plurality of conductive contacts on the second surface, and each having a distance to the first surface different from others of the plurality of second conductive metals.

2. The inductor structure of claim 1 , further comprising a third conductive pattern formed on a third surface of the semiconductor package structure, the third surface being opposite to the second surface, wherein the third conductive pattern is connected with the first conductive pattern.

3. The inductor structure of claim 2 , further comprising a fourth conductive pattern formed on a fourth surface of the semiconductor package structure, the fourth surface being opposite to the first surface, wherein the fourth conductive pattern is connected with the second conductive pattern and the third conductive pattern.

4. The inductor structure of claim 2 , further comprising a fifth conductive pattern formed on a fifth surface of the semiconductor package structure.

5. The inductor structure of claim 4 , further comprising a sixth conductive pattern formed on a sixth surface of the semiconductor package structure, the sixth surface being opposite to the fifth surface, wherein the sixth conductive pattern is connected with the first conductive pattern.

6. The inductor structure of claim 1 , wherein the first conductive pattern or the second conductive pattern is spiral.

7. The inductor structure of claim 1 , wherein the second conductive pattern comprises redistribution layers (RDL).

8. The inductor structure of claim 7 , wherein the first conductive pattern, the second conductive pattern, and the through via structure form a conductive loop.

9. The inductor structure of claim 7 , wherein the inductor structure comprises:
a first terminal receiving an input current from the integrated circuit; and
a second terminal sending an output current to the integrated circuit.

10. An inductor structure, comprising:
a first conductive pattern having a plurality of conductive metals;
a first dielectric layer encapsulating the first conductive pattern; and
a second conductive pattern on the first dielectric layer;
wherein the second conductive pattern is electrically connected with a first conductive metal and a second conductive metal of the first conductive pattern,
wherein the plurality of the conductive metals of the first conductive pattern are substantially parallel to each other, and the second conductive pattern is substantially perpendicular to the plurality of conductive metals of the first conductive pattern.

11. The inductor structure of claim 10 , wherein the second conductive pattern are electrically connected to the first conductive pattern through conductive contacts.

12. The inductor structure of claim 10 , wherein the conductive conducts are parallel to each other, and the first conductive pattern or the second conductive pattern is spiral.

13. The inductor structure of claim 10 , further comprising
a second dielectric layer on the first dielectric layer to encapsulate the second conductive pattern;
a third conductive pattern on the second dielectric layer; and
wherein the third conductive pattern is electrically connected with a third conductive metal and a fourth conductive metal of the first conductive pattern.

14. The inductor structure of claim 13 , wherein the third conductive pattern is substantially parallel to the second conductive pattern.

15. The inductor structure of claim 13 , wherein the third conductive pattern is electrically connected to the first conductive pattern through conductive contacts and wherein the conductive contacts are parallel to each other.

16. The inductor structure of claim 10 , wherein the first dielectric layer comprises molding compounds, pre-impregnated composite fibers, boro-phospho-slilicate-glass, silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass or any combination thereof.

17. The inductor structure of claim 10 , wherein the second conductive pattern comprises redistribution layers (RDL).

18. A semiconductor structure, comprising:
a carrier having a top surface;
an integrated circuit on the top surface of the carrier;
an inductor structure on the top surface of the carrier and adjacent to the integrated circuit, the inductor structure comprising:
a first surface coplanar with the top surface of the carrier;
a second surface parallel to the first surface;
a first conductive pattern on the first surface;
a second conductive pattern on the second surface,
wherein the first conductive pattern is connected with the second conductive pattern by a through via structure on a third surface, the third surface being perpendicular to the first surface and the second surface.

19. The semiconductor structure of claim 18 , wherein the first conductive pattern comprises a plurality of first conductive metal parallel to each other.

20. The semiconductor structure of claim 18 , wherein the second conductive pattern comprises a redistribution layer (RDL).

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Ting
• Lin In-Tsang
• Chen Vincent
• Wang Chuei-Tang
• Yu Chen-Hua

Classifications

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/695

  Organic materials · CPC title

• H10W70/692

  Ceramics or glasses · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W20/48

  Insulating materials thereof · CPC title