Nonvolatile memory device and method of reading the same

Patent metadata

Field	Value
Publication number	US-10043583-B2
Application number	US-201715447357-A
Country	US
Kind code	B2
Filing date	Mar 2, 2017
Priority date	Nov 14, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Provided are a nonvolatile memory device and a method of performing a sensing operation on the nonvolatile memory device. The nonvolatile memory device includes a control logic coupled to a memory cell array including strings. The control logic is configured to control a first weak-on voltage applied to an unselected string selection line and a second weak-on voltage applied to an unselected ground selection line during a setup interval of the sensing operation for sensing data from a selected string. The unselected string selection line and ground selection line are connected to a string selection transistor and a ground selection transistor, respectively, of a same unselected string. The selected string and the unselected string are connected to a same bit line. The first weak-on voltage and second weak-on voltage are respectively less than a threshold voltage of the string selection transistor and the ground selection transistor in the unselected string.

First claim

What is claimed is:

1. A nonvolatile memory device, comprising:
a memory cell array including strings connected to bit lines, word lines, string selection lines, and ground selection lines,
each of the strings including memory cells connected in series between a string selection transistor and a ground selection transistor; and

a control logic coupled to the memory cell array,
the control logic being configured to control a first weak-on voltage applied to an unselected string selection line among the string selection lines and a second weak-on voltage applied to an unselected ground selection line among the ground selection lines during a setup interval of a sensing operation for sensing data from a selected string among the strings,
the unselected string selection line and the unselected ground selection line being connected to the string selection transistor and the ground selection transistor, respectively, of a same unselected string among the strings,
the selected string and the unselected string being connected in common to a same one of the bit lines,
a level of the first weak-on voltage being less than a threshold voltage of the string selection transistor in the unselected string and greater than a ground voltage, and
a level of the second weak-on voltage being less than a threshold voltage of the ground selection transistor of the unselected string and greater than the ground voltage.

2. The nonvolatile memory device of claim 1 , wherein
the sensing operation is a read operation, and
the setup interval is a read setup interval.

3. The nonvolatile memory device of claim 1 , wherein
the sensing operation is a program verification operation, and the setup interval is a verification setup interval.

4. The nonvolatile memory device of claim 1 , wherein the level of the first weak-on voltage is different than the level of the second weak-on voltage.

5. The nonvolatile memory device of claim 1 , wherein
the level of the first weak-on voltage is equal to the level of the second weak-on voltage.

6. The nonvolatile memory device of claim 1 , wherein
the control logic is configured to control the first weak-on voltage applied to the unselected string selection line and the second weak-on voltage applied to the unselected ground selection line to have a same level during the setup interval.

7. The nonvolatile memory device of claim 6 , wherein
the sensing operation includes a sensing interval after the setup interval,
the control logic is configured to control a turn-off voltage applied to the unselected string selection line and the unselected ground selection line during the sensing interval.

8. The nonvolatile memory device of claim 7 , wherein
the control logic is configured to control the turn-off voltage applied to the unselected string selection line and the unselected ground selection line to begin at a same time during the sensing interval.

9. The nonvolatile memory device of claim 7 , wherein
the control logic is configured to control the turn-off voltage applied to the unselected string selection line and the unselected ground selection line during the sensing interval to begin at different times during the sensing interval.

10. The nonvolatile memory device of claim 1 , wherein
a pulse width of the first weak-on voltage is equal to a pulse width of the second weak-on voltage.

11. The nonvolatile memory device of claim 1 , wherein
the control logic is configured to control the first weak-on voltage applied to the unselected string selection line and the second weak-on voltage applied to the unselected ground selection line to have a same pulse-width during the setup interval.

12. The nonvolatile memory device of claim 1 , wherein
the level of the first weak-on voltage is less different from the level of the second weak-on voltage.

13. The nonvolatile memory device of claim 1 , wherein
the ground selection transistor in each of the strings is a first ground selection transistor,
each of the strings further includes a second ground selection transistor arranged so the first ground selection transistor is between the memory cells and the second ground selection transistor, and
the control logic is configured to control the second weak-on voltage applied to the unselected ground selection line that is connected to the first ground selection transistor of the same unselected string during the set up interval of the sensing operation.

14. A nonvolatile memory device, comprising:
a memory cell array including strings connected to bit lines,
each of the strings including memory cells connected in series between a string selection transistor and a ground selection transistor;

a row decoder connected to the strings through word lines, string selection lines, and ground selection lines;
a voltage generator connected to the row decoder; and
a control logic coupled to the row decoder and the voltage generator,
the control logic being configured to control the voltage generator and the row decoder to apply a first weak-on voltage to an unselected string selection line among the string selection lines and a second weak-on voltage to an unselected ground selection line among the ground selection lines during a setup interval of a sensing operation for sensing data from a selected string among the strings,
the unselected string selection line and the unselected ground selection line being connected to the string selection transistor and the ground selection transistor, respectively, of a same unselected string among the strings,
the selected string and the unselected string being connected in common to a same one of the bit lines,
a level of the first weak-on voltage being less than a threshold voltage of the string selection transistor in the unselected string and greater than a ground voltage, and a level of the second weak-on voltage being less than a threshold voltage of the ground selection transistor of the unselected string and greater than the ground voltage.

15. A control logic, comprising
a voltage controller configured to provide a row address and a column address to a row decoder and a page buffer, respectively, that are coupled to a memory cell array, based on a command, address, and control signal received from an external host,
the voltage controller being configured to generate a voltage control signal for controlling a voltage generator coupled to the row decoder, such that the voltage generator and the row decoder are controlled to apply a first weak-on voltage to an unselected string selection line and a second weak-on voltage to an unselected ground selection line during a setup interval of a sensing operation for sensing data from a selected string of the memory cell array,
the unselected string selection line and the unselected ground selection line being connected to a same unselected string,
the selected string and the unselected string being connected to a same bit line,

a level of the first weak-on voltage being less than a threshold voltage of a string selection transistor of the unselected string and greater than a ground voltage, and
a level of the second weak-on voltage being less than a threshold voltage of a ground selection transistor of the unselected string and greater than the ground voltage.

Assignees

• Nam Sang Wan
• Byeon Dae Seok
• Yoon Chi Weon
• Samsung Electronics Co Ltd

Inventors

• Nam Sang-Wan
• Byeon Dae-Seok
• Yoon Chi-Weon

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C8/10 Primary

  Decoders · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/32

  Timing circuits · CPC title