Method of reducing hot electron injection type of read disturb in dummy memory cells

Patent metadata

Field	Value
Publication number	US-9286994-B1
Application number	US-201514669247-A
Country	US
Kind code	B1
Filing date	Mar 26, 2015
Priority date	Jan 26, 2015
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In the unselected NAND string, a dummy memory cell is adjacent to a select gate transistor. During a read operation involving the selected NAND string, a voltage of the dummy memory cell is increased in two steps to minimize a gradient in a channel of the unselected NAND string between the dummy memory cell and the select gate transistor. During the first step, the select gate transistor is conductive so that the channel is connected to a driven bit line. During the second step, the select gate transistor is non-conductive. Voltages on unselected word lines can also be increased in two steps to set a desired channel boosting level in the unselected NAND string.

First claim

What is claimed is:

1. A method for performing a sensing operation in a memory device, the method comprising:
connecting a channel of an unselected NAND string in the memory device to a bit line while the bit line is at a driven voltage, wherein the bit line is connected to a selected NAND string, a select gate line is connected to a drain-side select gate transistor at a drain-side of the unselected NAND string and a drain-side select gate transistor at a drain-side of the selected NAND string, a first dummy word line is connected to a first dummy memory cell in the unselected NAND string adjacent to the drain-side select gate transistor of the unselected NAND string and to a first dummy memory cell in the selected NAND string adjacent to the drain-side select gate transistor of the selected NAND string, a selected word line is connected to a selected memory cell in the selected NAND string and to a corresponding unselected memory cell in the unselected NAND string, unselected word lines are connected to unselected memory cells in the selected NAND string and to corresponding unselected memory cells in the unselected NAND string, and the connecting comprises requesting a voltage driver of the select gate line to provide a step up of a voltage on the select gate line, requesting a voltage driver of the first dummy word line to provide a first step up of a voltage on the first dummy word line, and requesting a voltage driver of the unselected word lines to provide a first step up of a voltage on the unselected word lines;
after the connecting, disconnecting the channel of the unselected NAND string from the bit line, the disconnecting comprising requesting the voltage driver of the select gate line to provide a step down of the voltage on the select gate line; and
while the channel of the unselected NAND string is disconnected from the bit line:
requesting the voltage driver of the unselected word lines to provide a second step up of the voltage of the unselected word lines,
requesting the voltage driver of the first dummy word line to provide a second step up of the voltage of the first dummy word line,
requesting a voltage driver of the selected word line to provide one or more voltages on the selected word line, and
sensing the selected memory cell while the selected word line is at the one or more voltages.

2. The method of claim 1 , wherein:
the second step up of the voltage on the first dummy word line occurs after the second step up of the voltage on the unselected word lines.

3. The method of claim 2 , wherein:
a time interval between the second step up of the voltage on the first dummy word line and the second step up of the voltage on the unselected word lines is at least as long as a time interval in which the channel of the unselected NAND string is connected to the bit line during the connecting.

4. The method of claim 3 , wherein:
the time interval in which the channel of the unselected NAND string is connected to the bit line during the connecting is a time interval in which a control gate-to-drain voltage of the drain-side select gate transistor of the drain-side of the unselected NAND string exceeds a threshold voltage of the drain-side select gate transistor of the drain-side of the unselected NAND string.

5. The method of claim 1 , wherein:
the step up of the voltage on the select gate line occurs concurrently with the first step up of the voltage on the first dummy word line and the first step up of the voltage on the unselected word lines.

6. The method of claim 1 , wherein:
the step up of the voltage on the select gate line occurs before the first step up of the voltage on the first dummy word line and the first step up of the voltage on the unselected word lines.

7. The method of claim 1 , wherein:
a time interval between the step up of the voltage of the select gate line and the step down of the voltage of the select gate line is insufficient for the voltage of the select gate line to reach a steady state voltage.

8. The method of claim 1 , wherein:
a level of the first step up of the voltage on the first dummy word line and a level of the second step up of the voltage on the first dummy word line increase periodically over a lifetime of the memory device.

9. The method of claim 1 , further comprising:
measuring an increase in a threshold voltage distribution of a set of dummy memory cells connected to the first dummy word line; and
increasing a level of the first step up of the voltage on the first dummy word line and a level of the second step up of the voltage on the first dummy word line in response to the measuring.

10. The method of claim 1 , wherein:
a second dummy word line is connected to a second dummy memory cell in the unselected NAND string and to a second dummy memory cell in the selected NAND string;
the second dummy word line in the unselected NAND string is adjacent to the first dummy memory cell of the unselected NAND string;
the second dummy word line in the selected NAND string is adjacent to the first dummy memory cell of the selected NAND string;
threshold voltages of the second dummy memory cell of the unselected NAND string and the second dummy memory cell of the selected NAND string are higher than threshold voltages of the first dummy memory cell of the unselected NAND string and the first dummy memory cell of the selected NAND string;
the connecting comprises requesting a voltage driver of the second dummy word line to provide a first step up of a voltage on the second dummy word line concurrent with the first step up of the voltage on the first dummy word line; and
while the channel of the unselected NAND string is disconnected from the bit line, requesting the voltage driver of the second dummy word line to provide a second step up of the voltage of the second dummy word line concurrent with the second step up of the voltage on the first dummy word line.

11. A non-volatile memory device, comprising:
a selected NAND string comprising a drain-side select gate transistor at a drain-side of the selected NAND string, a first dummy memory cell adjacent to the drain-side select gate transistor of the selected NAND string, a selected memory cell and unselected memory cells;
an unselected NAND string comprising a drain-side select gate transistor at a drain-side of the unselected NAND string, a first dummy memory cell adjacent to the drain-side select gate transistor of the unselected NAND string, an unselected memory cell corresponding to the selected memory cell and other unselected memory cells;
a select gate line connected to the drain-side select gate transistor of the selected NAND string and the drain-side select gate transistor of the unselected NAND string;
a first dummy word line connected to the first dummy memory cell of the selected NAND string and the first dummy memory cell of the unselected NAND string;
a selected word line connected to the selected memory cell and the corresponding unselected memory cell;
unselected word lines connected to the unselected memory cells of the selected NAND string and the other unselected memory cells of the unselected NAND string;
a bit line connected to the selected NAND string and to the unselected NAND string; and
a control circuit, the control circuit is configured to:
provide one increase of a voltage on the select gate line, one increase of a voltage on the first dummy word line and one increase of voltages of the unselected word lines while the bit line is at a driven voltage;
subsequently provide a decrease of the voltage on the select gate line;
subsequently provide another increase of the voltage on the first dummy word line and another increase of the vol

Assignees

• Sandisk Technologies Inc

Inventors

• Chen hong-yan
• Dong Yingda
• Zhao Wei

Classifications

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title