Abnormal interrupt request processing

Patent metadata

Field	Value
Publication number	US-10042791-B2
Application number	US-201715588246-A
Country	US
Kind code	B2
Filing date	May 5, 2017
Priority date	Jul 11, 2013
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

First claim

What is claimed is:

1. A microcomputer comprising:
an interrupt controller including an interrupt request circuit which holds a first interrupt request flag and a second interrupt request flag, and which outputs an interrupt signal in response to one of a first interrupt request and a second interrupt request;
a central processing unit (CPU) which outputs an interrupt acknowledgment signal based on the interrupt signal; and
a timer which generates, periodically at an interval, a test interrupt request, wherein
the interrupt controller sets the first interrupt request flag in the interrupt request circuit in response to the first interrupt request, resets the first interrupt request flag set in the interrupt request circuit in response to the interrupt acknowledgment signal originated with the first interrupt request, sets the second interrupt request flag in the interrupt request circuit in response to the second interrupt request, and resets the second interrupt request flag set in the interrupt request circuit in response to the interrupt acknowledgment signal originated with the second interrupt request, and
the CPU refers to the first and second interrupt request flags held in the interrupt request circuit based on the test interrupt request, and determines that there is an abnormality in an interrupt control system when at least one of the first interrupt request flag and the second interrupt flag is set a plurality of times in succession.

2. The microcomputer according to claim 1 , wherein the CPU controls the interval at which the test interrupt request is generated periodically.

3. The microcomputer according to claim 1 , wherein
the interrupt controller comprises a first interrupt controller,
the interrupt request circuit comprises a first interrupt request circuit,
the interrupt signal comprises a first interrupt signal,
the interrupt controller further includes a first priority and mask control logic circuit which generates, based on a mask setting and priority level set, the first interrupt signal in response to one of the first interrupt request and the second interrupt request,
the interrupt controller further comprises a second interrupt controller which includes a second interrupt request circuit which holds a third interrupt request flag, and a second priority and mask control logic circuit which generates, based on a mask setting and priority level set, a second interrupt signal in response to one of the first interrupt signal and a third interrupt request,
the CPU outputs the interrupt acknowledgment signal based on the second interrupt signal,
the second interrupt controller sets the third interrupt request flag in the second interrupt request circuit in response to the third interrupt request, and resets the third interrupt request flag set in the second interrupt request circuit in response to the interrupt acknowledgment signal originated with the third interrupt request, and
the CPU refers to the third interrupt request flag held in the second interrupt request circuit based on the test interrupt request, and determines that there is an abnormality in the interrupt control system when the third interrupt request flag is set a plurality of times in succession.

4. The microcomputer according to claim 3 , wherein the second interrupt controller outputs, to the CPU, a vector corresponding to the third interrupt request in response to the interrupt acknowledgment signal originated with the third interrupt request.

5. The microcomputer according to claim 3 , wherein
the interrupt controller further comprises a third interrupt controller which includes a third interrupt request circuit which holds a fourth interrupt request flag, and which outputs a third interrupt signal in response to a fourth interrupt request,
the second priority and mask control logic circuit generates, based on a mask setting and priority level set, the second interrupt signal in response to one of the first interrupt signal, the third interrupt request and the third interrupt signal,
the third interrupt controller sets the fourth interrupt request flag in the third interrupt request circuit in response to the fourth interrupt request, and resets the fourth interrupt request flag set in the third interrupt request circuit in response to the interrupt acknowledgment signal originated with the fourth interrupt request, and
the CPU refers to the fourth interrupt request flag held in the third interrupt request circuit based on the test interrupt request, and determines that there is an abnormality in the interrupt control system when the fourth interrupt request flag is set a plurality of times in succession.

6. The microcomputer according to claim 5 , wherein
the third interrupt controller further includes a third priority and mask control logic circuit which generates, based on a mask setting and priority level set, the third interrupt signal in response to one of the fourth interrupt request and the test interrupt request, and
the CPU refers to the first, second, third and fourth interrupt request flags based on the second interrupt signal originated with the test interrupt request.

7. The microcomputer according to claim 6 , wherein a priority of the fourth interrupt request is lower than those of the first and second interrupt requests.

8. The microcomputer according to claim 6 , wherein
the timer comprises a first timer,
the test interrupt request comprises a first test interrupt request,
the microcomputer further comprises a second timer which generates, periodically at an interval, a second test interrupt request, and a comparator,
the third interrupt controller further includes a fourth priority and mask control logic circuit which generates, based on a mask setting and priority level set, a fourth interrupt signal in response to one of the fourth interrupt request and the second test interrupt request, and
the comparator compares the third interrupt signal with the fourth interrupt signal.

9. The microcomputer according to claim 6 , further comprising a selector which receives the first and second interrupt requests, wherein
when the CPU refers to the first interrupt request flag to determine that there is an abnormality in the interrupt control system, the CPU generates a select signal for selecting the first interrupt request,
the selector selects and outputs the first interrupt request to the third interrupt controller according to the select signal, and
the third priority and mask control logic circuit, based on the mask setting and priority level set, the third interrupt signal in response to one of the fourth interrupt request, the test interrupt request and the first interrupt request.

Assignees

• Renesas Electronics Corp

Inventors

• Hirade Takuya
• Tsuboi Yukitoshi
• Okuda Ryosuke

Classifications

• G06F11/2231 Primary

  to test interrupt circuits · CPC title

• G06F2211/002

  Bus · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F11/2273

  Test methods · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic