Abnormal interrupt request processing

Patent metadata

Field	Value
Publication number	US-9678900-B2
Application number	US-201414328154-A
Country	US
Kind code	B2
Filing date	Jul 10, 2014
Priority date	Jul 11, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

First claim

What is claimed is:

1. A microcomputer comprising:
a central processing unit; and
an interrupt controller, wherein
the central processing unit is configured to refer to an interrupt request flag held by the interrupt controller, in response to a test interrupt request generated periodically at a predetermined interval, and determine that there is an abnormality when successively detecting multiple times that the interrupt request flag is in a set state, and
the interrupt controller includes a first interrupt controller to which the test interrupt request is given and a second interrupt controller having the interrupt request flag to be referred to by the central processing unit in response to the test interrupt request.

2. The microcomputer according to claim 1 , further comprising:
first and second redundant test interrupt request generation circuits configured to generate first and second redundant test interrupt requests, respectively; and
a determination circuit, wherein
the first interrupt controller processes the first redundant test interrupt request to output a first interrupt signal, and processes the second redundant test interrupt request to output a second interrupt signal, and
the determination circuit receives the first and second interrupt signals to determine whether the first and second interrupt signals coincide with each other.

3. The microcomputer according to claim 1 , further comprising a selector configured to select an interrupt request to be input to the second interrupt controller and to input the interrupt request to the first interrupt controller, wherein
the central processing unit controls the selector to input the interrupt request to the first interrupt controller, the interrupt request corresponding to the interrupt request flag and being generated when the central processing unit determines that there is an abnormality based on that interrupt request flag.

4. A microcomputer comprising:
a central processing unit; and
an interrupt controller, wherein
the central processing unit is configured to refer to an interrupt request flag held by the interrupt controller, in response to a test interrupt request generated periodically at a predetermined interval, and determine that there is an abnormality when successively detecting multiple times that the interrupt request flag is in a set state, and
the interrupt controller includes:
a master interrupt controller configured to be capable of receiving a plurality of interrupt requests and configured to process an input interrupt request to output an interrupt signal to the central processing unit; and
a slave interrupt controller configured to be capable of receiving a plurality of interrupt requests and configured to process an input interrupt request to output an interrupt request signal to the master interrupt controller.

5. The microcomputer according to claim 4 , wherein
the slave interrupt controller holds a slave interrupt request flag in response to the test interrupt request, and is configured to send an interrupt request to the master interrupt controller,
the master interrupt controller holds a corresponding master interrupt request flag in response to the interrupt request from the slave interrupt controller,
the central processing unit refers to the slave interrupt request flag and the corresponding master interrupt request flag, and determines that there is an abnormality when successively detecting multiple times that the slave interrupt request flag and the corresponding master interrupt request flag are in a set state.

6. The microcomputer according to claim 5 ,
wherein the central processing unit determines:
that there is an abnormality inside the slave interrupt controller or in a path from the master interrupt controller to an input of the central processing unit when successively detecting multiple times that the slave interrupt request flag and the corresponding master interrupt request flag are in a set state; and
that there is an abnormality in a path from the slave interrupt controller to an input of the master interrupt controller when successively detecting multiple times that the slave interrupt request flag are in a set state and the corresponding master interrupt request flag are not in a set state.

7. The microcomputer according to claim 4 , wherein the test interrupt request is input to the master interrupt controller.

8. The microcomputer according to claim 4 , wherein the slave interrupt controller has a first slave interrupt controller to which the test interrupt request is given and a second slave interrupt controller holding an interrupt request flag to be referred to by the central processing unit in response to the test interrupt request.

9. The microcomputer according to claim 8 , wherein further comprising:
first and second redundant test interrupt request generation circuits configured to generate first and second redundant test interrupt requests, respectively; and
a determination circuit, wherein
the first slave interrupt controller processes the first redundant test interrupt request to output a first interrupt signal, and processes the second redundant test interrupt request to output a second interrupt signal,
the determination circuit receives the first and second interrupt signals to determine whether the first and second interrupt signals coincide with each other, and
the master interrupt controller processes an AND signal of the first and second interrupt signals as one interrupt request.

10. The microcomputer according to claim 8 , further comprising a selector configured to select an interrupt request to be input to the second slave interrupt controller and to input the interrupt request to the first slave interrupt controller, wherein
the central processing unit controls the selector to input the interrupt request to the first slave interrupt controller, the interrupt request corresponding to the interrupt request flag and being generated when the central processing unit determines that there is an abnormality based on that interrupt request flag.

11. The microcomputer according to claim 4 , wherein
the master interrupt controller comprises first and second redundant master interrupt controllers configured to operate in parallel to each other to have a lock-step architecture so that an abnormality is detectable when there is a difference in operation between the first redundant master interrupt controller and the second redundant master interrupt controller, and
the central processing unit comprises first and second redundant central processing units configured to operate in parallel to each other to have a lock-step architecture so that an abnormality is detectable when there is a difference in operation between the first redundant central processing unit and the second redundant central processing unit.

12. A microcomputer comprising:
a central processing unit; and
an interrupt controller, wherein
the central processing unit is configured to refer to an interrupt request flag held by the interrupt controller, in response to a test interrupt request generated periodically at a predetermined interval, and determine that there is an abnormality when successively detecting multiple times that the interrupt request flag is in a set state, and
the interrupt controller includes a first interrupt controller to which the test interrupt request and a first interrupt request are given and a second interrupt controller to which a second interrupt request is given,
a test interrupt request generation circuit comprises first and second redundant test interrupt request generation circuits configured to generate first and

Assignees

• Renesas Electronics Corp

Inventors

• Hirade Takuya
• Tsuboi Yukitoshi
• Okuda Ryosuke

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F11/2273

  Test methods · CPC title

• G06F11/2231 Primary

  to test interrupt circuits · CPC title

• G06F2211/002

  Bus · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title