System-on-chip having a symmetric multi-processor and method of determining a maximum operating clock frequency for the same

Patent metadata

Field	Value
Publication number	US-10042731-B2
Application number	US-201414453106-A
Country	US
Kind code	B2
Filing date	Aug 6, 2014
Priority date	Nov 11, 2013
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

A system-on-chip includes a symmetric multi-processor including a plurality of cores, each configured to operate in a high performance operating mode and a low performance operating mode. The system-on-chip further includes a clock management unit configured to provide an operating clock signal to the symmetric multi-processor, a state management unit configured to monitor operating states of the cores, a temperature management unit configured to monitor a temperature of the symmetric multi-processor, and a symmetric multi-processor control unit configured to determine the operating clock signal and the operating states of the cores based on a workload of the symmetric multi-processor. The symmetric multi-processor control unit is further configured to differentially determine a maximum operating clock frequency for the cores based on the temperature and the operating states of the cores, which indicate a quantity of cores that are currently in operation.

First claim

What is claimed is:

1. A system-on-chip, comprising:
a symmetric multi-processor comprising a plurality of cores, wherein each core is configured to operate in a high performance operating mode and a low performance operating mode;
a clock management unit configured to provide an operating clock signal to the symmetric multi-processor;
a state management unit configured to monitor operating states of the cores;
a temperature management unit configured to monitor a temperature of the symmetric multi-processor; and
a symmetric multi-processor control unit configured to determine the operating clock signal and the operating states of the cores based on a workload of the symmetric multi-processor, and to differentially determine a maximum operating clock frequency for the cores based on the temperature and the operating states of the cores,
wherein the operating states of the cores indicate a quantity of cores of the symmetric multi-processor that is currently in operation,
wherein, at each of a first given temperature and a second given temperature in a high temperature range, the maximum operating clock frequency of all of the cores currently in operation is different when the quantity of cores currently in operation is equal to a first value compared to when the quantity of cores currently in operation is equal to a second value,
wherein the maximum operating clock frequency of all of the cores currently in operation when the quantity of cores is equal to the first value at the first given temperature is different from the maximum operating clock frequency of all of the cores currently in operation when the quantity of cores is equal to the first value at the second given temperature, and the maximum operating clock frequency of all of the cores currently in operation when the quantity of cores is equal to the second value at the first given temperature is different from the maximum operating clock frequency of all of the cores currently in operation when the quantity of cores is equal to the second value at the second given temperature,
wherein the maximum operating clock frequency of the cores is differentially managed in the high temperature range, and the maximum operating clock frequency of the cores is the same at all temperatures in a low temperature range.

2. The system-on-chip of claim 1 , wherein the symmetric multi-processor control unit is configured to differentially determine the maximum operating clock frequency for the cores while the symmetric multi-processor is operating.

3. The system-on-chip of claim 1 , wherein each of the cores comprises:
a first sub-core configured to operate in the high performance operating mode, wherein the first sub-core constitutes a first cluster of the symmetric multi-processor; and
a second sub-core configured to operate in the low performance operating mode, wherein the second sub-core constitutes a second cluster of the symmetric multi-processor.

4. The system-on-chip of claim 3 , wherein the symmetric multi-processor control unit is configured to differentially determine the maximum operating clock frequency for the cores based on the temperature and the operating states of the cores when the temperature is between a first threshold temperature and a second threshold temperature, wherein the second threshold temperature is higher than the first threshold temperature.

5. The system-on-chip of claim 4 , wherein the symmetric multi-processor control unit is configured to determine the maximum operating clock frequency for the cores to be a maximum tolerance value when the temperature is lower than the first threshold temperature.

6. The system-on-chip of claim 4 , wherein the symmetric multi-processor control unit is configured to change a mode of at least one of the cores from the high performance operating mode to the low performance operating mode when the temperature is higher than the second threshold temperature.

7. The system-on-chip of claim 1 , wherein the system-on-chip is an application processor.

8. The system-on-chip of claim 7 , wherein the state management unit is a power management configured to monitor the operating states of the cores based on a voltage supplied to the application processor.

9. A system-on-chip, comprising:
a symmetric multi-processor comprising a plurality of cores;
a clock management unit configured to provide an operating clock signal to the symmetric multi-processor;
a state management unit configured to monitor operating states of the cores, wherein the operating states of the cores indicate a quantity of cores of the symmetric multi-processor that is currently in an active state;
a temperature management unit configured to monitor a temperature of the symmetric multi-processor; and
a symmetric multi-processor control unit configured to determine the operating clock signal and the operating states of the cores based on a workload of the symmetric multi-processor, and to differentially determine a maximum operating clock frequency for the cores based on the temperature and the quantity of cores that is currently in the active state,
wherein, at each of a first given temperature and a second given temperature in a high temperature range, the maximum operating clock frequency of the cores that are currently in the active state is different when the quantity of cores currently in the active state is equal to a first value compared to when the quantity of cores currently in the active state is equal to a second value,
wherein the maximum operating clock frequency of the cores currently in the active state when the quantity of cores is equal to the first value at the first given temperature is different from the maximum operating clock frequency of the cores currently in the active state when the quantity of cores is equal to the first value at the second given temperature, and the maximum operating clock frequency of the cores currently in the active state when the quantity of cores is equal to the second value at the first given temperature is different from the maximum operating clock frequency of the cores currently in the active state when the quantity of cores is equal to the second value at the second given temperature,
wherein the maximum operating clock frequency of the cores is differentially managed in the high temperature range, and the maximum operating clock frequency of the cores is the same at all temperatures in a low temperature range.

10. The system-on-chip of claim 9 , wherein the symmetric multi-processor control unit is configured to differentially determine the maximum operating clock frequency for the cores while the symmetric multi-processor is operating.

11. The system-on-chip of claim 9 , wherein the symmetric multi-processor control unit is configured to differentially determine the maximum operating clock frequency for the cores based on the temperature and the quantity of cores that is currently in the active state when the temperature is between a first threshold temperature and a second threshold temperature, wherein the second threshold temperature is higher than the first threshold temperature.

12. The system-on-chip of claim 11 , wherein the symmetric multi-processor control unit is configured to determine the maximum operating clock frequency for the cores to be a maximum tolerance value when the temperature is lower than the first threshold temperature.

13. The system-on-chip of claim 11 , wherein the symmetric multi-processor control unit is configured to change a mode of at least one of the cores from an operating mode to a non-operating mode when the temperature is higher than the second threshold temperature.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jong-Lae
• Lee Byeong-Jun

Classifications

• G06F11/3058 Primary

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F1/206

  comprising thermal management · CPC title

• G06F2201/81

  Threshold · CPC title

• G06F11/3006

  where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50) · CPC title

• Y02D10/16

  Cross-Sectional Technologies · mapped topic