Dynamically computing an electrical design point (EDP) for a multicore processor

Patent metadata

Field	Value
Publication number	US-9436245-B2
Application number	US-201213997757-A
Country	US
Kind code	B2
Filing date	Mar 13, 2012
Priority date	Mar 13, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core activity pattern of the cores and power consumption information of a unit power table. In one embodiment, the core activity pattern can indicate, for each core, an activity level and a logic unit state of the corresponding core. Further, the unit power table can be dynamically computed based on a temperature of the processor. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores each to independently execute instructions, each of the plurality of cores to operate at an independent voltage and frequency; and
a power controller coupled to the plurality of cores and including first logic to group the plurality of cores into a first group of cores corresponding to inactive cores, a second group of cores corresponding to cores to operate at or below a guaranteed maximum operating frequency, and a third group of cores corresponding to cores to request a turbo mode frequency, determine a power consumption for the first and second groups of cores, determine an available power budget for the third group of cores based on the determined power consumption for the first and second groups of cores, and perform an iterative search for a maximum permitted turbo mode frequency for the third group of cores based at least in part on information in a unit power table including a plurality of entries, each entry to associate a turbo mode frequency with a first power consumption level at which a core is to operate when first circuitry of the core is to not execute and a second power consumption level at which the core is to operate when the first circuitry is to execute.

2. The processor of claim 1 , wherein the first logic is to dynamically calculate the plurality of entries in the unit power table based on a temperature of the processor.

3. The processor of claim 2 , wherein the first logic is to re-calculate the plurality of entries in the unit power table if the processor temperature changes by a threshold amount.

4. The processor of claim 1 , wherein the first logic is to calculate a sum of power consumption for the third group of cores at a possible turbo mode frequency, and compare the sum to the available power budget.

5. The processor of claim 4 , wherein the first logic is to reduce the possible turbo mode frequency to a lower turbo mode frequency if the sum is greater than the available power budget.

6. The processor of claim 4 , wherein the first logic is to iteratively calculate the sum and perform the comparison until the possible turbo mode frequency is greater than a requested turbo mode frequency of any of the third group of cores.

7. The processor of claim 6 , wherein the first logic is to terminate the iterative calculation and comparison when the sum is greater than or equal to zero and less than a minimum power threshold.

8. A system comprising:
a multicore processor including a plurality of cores each to independently execute instructions and to operate at an independent voltage and frequency, and a power control unit (PCU) to dynamically limit a maximum permitted turbo mode frequency of the plurality of cores based on a core activity pattern of the plurality of cores that indicates for each of the plurality of cores an activity level and a logic unit state of the corresponding core and power consumption information of a unit power table, wherein the PCU is to dynamically compute the power consumption information of the unit power table based on a temperature of the multicore processor, the unit power table including a plurality of entries, each entry to associate a turbo mode frequency with a first power consumption level at which a core is to operate when a first logic unit of the core is to not execute and a second power consumption level at which the core is to operate when the first logic unit is to execute.

9. The system of claim 8 , wherein the PCU includes a power consumption calculator to dynamically compute the unit power table when a temperature of the multicore processor exceeds a threshold.

10. The system of claim 9 , wherein the power consumption calculator is to calculate the first power consumption level and the second power consumption level for each of a plurality of turbo mode frequencies.

11. The system of claim 8 , wherein the power control unit includes an electrical design point (EDP) clip logic to dynamically limit the maximum permitted turbo mode frequency based on the power consumption information of the unit power table by use of the core activity pattern stored in a core activity array, and a plurality of processor constraint values.

12. The system of claim 8 , wherein the PCU further includes a core frequency controller to assign an operating frequency to at least one of the plurality of cores based on the maximum permitted turbo mode frequency.

13. A processor comprising:
a plurality of cores each to independently execute instructions, each of the plurality of cores to operate at an independent voltage and frequency; and
a power controller coupled to the plurality of cores and including a first logic to group the plurality of cores into a first group of cores corresponding to inactive cores, a second group of cores corresponding to cores to operate at or below a guaranteed maximum operating frequency, and a third group of cores corresponding to cores to request a turbo mode frequency and determine a power consumption for the first and second groups of cores, a second logic to determine an available power budget for the third group of cores based on the determined power consumption for the first and second groups of cores, and a third logic to search for a maximum permitted turbo mode frequency for the third group of cores, wherein the power controller includes a unit power table having a plurality of entries, each entry to associate a turbo mode frequency with a first power consumption level at which a core is to operate when first circuitry of the core is to not execute and a second power consumption level at which the core is to operate when the first circuitry is to execute.

14. The processor of claim 13 , wherein the second logic is to dynamically calculate the plurality of entries in the unit power table based on a temperature of the processor.

15. The processor of claim 14 , wherein the second logic is to re-calculate the plurality of entries in the unit power table if the processor temperature changes by a threshold amount.

16. The processor of claim 13 , wherein the second logic is to calculate a sum of power consumption for the third group of cores at a possible turbo mode frequency, and compare the sum to the available power budget.

Assignees

• Bhandaru Malini K
• Dehaemer Eric J
• Shrall Jeremy J
• Intel Corp

Inventors

• Bhandaru Malini K
• Dehaemer Eric J
• Shrall Jeremy J

Classifications

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic

• G06F1/324

  by lowering clock frequency · CPC title