Data buffer spare architectures for dual channel serial interface memories

Patent metadata

Field	Value
Publication number	US-10042726-B2
Application number	US-201715841798-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Nov 29, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.

First claim

What is claimed is:

1. A computer-implemented method for implementing a spare data buffer in a memory comprising a first dual-inline memory module (DIMM) and a second DIMM, the method comprising:
detecting, by a processor, a failed data buffer in the first DIMM of the memory, wherein the first DIMM comprises a first plurality of data buffers, and wherein the failed data buffer is one of the first plurality of data buffers;
enabling, by the processor, the spare data buffer in the first DIMM, wherein the spare data buffer is another one of the first plurality of data buffers; and
extending, by the processor, a buffer communication bus to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer,
wherein the first DIMM comprises the first plurality of data buffers and at least one first spare data buffer, wherein the second DIMM comprises a second plurality of data buffers and at least one second spare data buffer, wherein the first DIMM comprises a first register clock driver, and wherein the second DIMM comprises a second register clock driver.

Assignees

• IBM

Inventors

• Kim Kyu-Hyoun
• Maule Warren E
• Mcilvain Kevin M
• Sethuraman Saravanan

Classifications

• G06F2201/805

  Real-time · CPC title

• G06F11/2094 Primary

  Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F11/1666 Primary

  where the redundant component is memory or memory area · CPC title