Incremental preloading in an analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10038452-B2
Application number	US-201715649313-A
Country	US
Kind code	B2
Filing date	Jul 13, 2017
Priority date	Sep 23, 2016
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

First claim

The invention claimed is:

1. A method of improving digital-to-analog converter (DAC) resolution in a DAC including a thermometer encoded array having logically adjacent capacitive cells corresponding to different bit positions of an input digital control word by temporally ordering the sequential loading of capacitive cells in the DAC to reduce transient out-of-range voltages and associated loss of signal charge, the method comprising:
loading onto a first cell having a logical position in the array of capacitive cells determined by a logical midpoint of the thermometer encoded array, a charge associated with a decoded most significant bit (MSB) decision; and
then loading onto a second cell on a first logical side of the logical midpoint, a charge associated with a decoded second bit decision, and loading onto a third cell on a second logical side of the logical midpoint different from the first logical side, a charge associated with a decoded third bit decision.

2. The method of claim 1 wherein the second cell is logically adjacent to the first cell and the third cell is logically adjacent to the first cell.

3. The method of claim 1 wherein the second cell is the logically furthest cell from the logical midpoint on the first logical side and the third cell is the logically furthest cell from the logical midpoint on the second logical side.

4. The method of claim 1 wherein the decoded MSB decision corresponds to a majority cell decision included with a majority of the capacitive cells sharing a like charge in the sequence of logically adjacent capacitive cells.

5. The method of claim 4 wherein the charge loaded onto the second cell corresponds to a majority cell decision included with a majority of the capacitive cells sharing a like charge in the sequence of logically adjacent capacitive cells, and the charge loaded onto the third cell corresponds to a minority cell decision included with a minority of the capacitive cells sharing a like charge in the sequence of adjacent capacitive cells.

6. The method of claim 4 wherein the charge loaded onto the second cell corresponds to a majority cell decision included with a majority of the capacitive cells sharing a like charge in the sequence of logically adjacent capacitive cells, and the charge loaded onto the third cell corresponds to a majority cell decision included with a minority of the capacitive cells sharing a like charge in the sequence of adjacent capacitive cells.

7. The method of claim 1 comprising determining the most significant bit decision, the second bit decision, and the third bit decision using a separate auxiliary ADC.

8. The method of claim 1 comprising then loading onto a fourth cell on the first logical side of the logical midpoint, a charge associated with a decoded fourth bit decision, and loading onto a fifth cell on the second logical side of the logical midpoint, a charge associated with a decoded fifth bit decision.

9. The method of claim 8 wherein the second cell is logically adjacent to the first cell, the third cell is logically adjacent to the first cell, the fourth cell is logically adjacent to the second cell, and the fifth cell is logically adjacent to the third cell.

10. The method of claim 8 wherein the second cell is the logically furthest cell from the logical midpoint on the first logical side and, third cell is the logically furthest cell from the logical midpoint on the second logical side, the fourth cell is logically adjacent to the second cell, and the fifth cell is logically adjacent to the third cell.

11. A system for improving digital-to-analog converter (DAC) resolution in a DAC including a thermometer encoded array having logically adjacent capacitive cells corresponding to different bit positions of an input digital control word by temporally ordering the sequential loading of capacitive cells in the DAC to reduce transient out-of-range voltages and associated loss of signal charge, the system comprising:
a first cell having a logical position in an array of capacitive cells determined by a logical midpoint of the thermometer encoded array;
a second cell on a first logical side of the logical midpoint and a third cell on a second logical side of the logical midpoint different from the first logical side; and
control circuitry configured to (i) load a charge associated with a decoded most significant bit (MSB) decision onto the first cell, and (ii) then load a charge associated with a decoded second bit decision onto the second cell and load a charge associated with a decoded third bit decision onto the third cell.

12. The method of claim 11 wherein the second cell is logically adjacent to the first cell and the third cell is logically adjacent to the first cell.

13. The method of claim 11 wherein the second cell is the logically furthest cell from the logical midpoint on the first logical side and the third cell is the logically furthest cell from the logical midpoint on the second logical side.

14. The system of claim 11 wherein the decoded MSB decision corresponds to a majority cell decision included with a majority of the capacitive cells sharing a like charge in the sequence of logically adjacent capacitive cells.

15. The system of claim 14 wherein the charge loaded onto the second cell corresponds to a majority cell decision included with a majority of the capacitive cells sharing a like charge in the sequence of logically adjacent capacitive cells, and the charge loaded onto the third cell corresponds to a minority cell decision included with a minority of the capacitive cells sharing a like charge in the sequence of adjacent capacitive cells.

16. The system of claim 14 wherein the charge loaded onto the second cell corresponds to a majority cell decision included with a majority of the capacitive cells sharing a like charge in the sequence of logically adjacent capacitive cells, and the charge loaded onto the third cell corresponds to a majority cell decision included with a minority of the capacitive cells sharing a like charge in the sequence of adjacent capacitive cells.

17. The system of claim 11 comprising a separate auxiliary ADC configured to predetermine the most significant hit decision, the second bit decision, and the third bit decision.

18. The system of claim 11 wherein the controller is configured to then load onto the first logical side of the logical midpoint, a charge associated with a decoded fourth bit decision, and load onto a fifth cell on the second logical side of the logical midpoint, a charge associated with a decoded fifth bit decision.

19. The system of claim 18 wherein the second cell is logically adjacent to the first cell, the third cell is logically adjacent to the first cell, the fourth cell is logically adjacent to the second cell, and the fifth cell is logically adjacent to the third cell.

20. The system of claim 18 wherein the second cell is the logically furthest cell from the logical midpoint on the first logical side and, third cell is the logically furthest cell from the logical midpoint on the second logical side, the fourth cell is logically adjacent to the second cell, and the fifth cell is logically adjacent to the third cell.

Assignees

• Analog Devices Inc

Inventors

• Chen Baozhen
• Guthrie Edward C
• Coln Michael C W
• Maddox Mark D

Classifications

• H03M1/0651

  by selecting the quantisation value generators in a non-sequential order, e.g. symmetrical · CPC title

• H03M1/806

  with equally weighted capacitors which are switched by unary decoded digital signals · CPC title

• H03M1/0836 Primary

  of phase error, e.g. jitter · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title