System for controlliing gatings of a multi-core processor

Patent metadata

Field	Value
Publication number	US-10038430-B2
Application number	US-201313747023-A
Country	US
Kind code	B2
Filing date	Jan 22, 2013
Priority date	Nov 9, 2012
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A system for controlling gatings of a multi-core processor, the system includes a pulse width modulation generator for generating a control square wave; and a phase shifter for shifting a phase of the control square wave to generate control square waves with different phases, and respectively inputting the control square waves with the different phases to a gating of each of multiple processing engines in the multi-core processor. A multi-core processor is provided that includes multiple processing engines. Each processing engine includes a gating, and a system for controlling the gating. Accordingly, in the multi-core processor, the load to be processed in a certain period of a working cycle can be averaged to be processed in a longer period of the working cycle. Consequently, current noise and voltage noise and temperature growth due to the load change can be reduced.

First claim

The invention claimed is:

1. A system for controlling gatings of a multi-core processor, including:
a pulse width modulation generator for generating a control square wave; and
a phase shifter for shifting a phase of the control square wave to generate control square waves with different phases, and respectively inputting the control square waves with the different phases to a gating of each of multiple processing engines in the multi-core processor.

2. The system according to claim 1 , wherein the phases of the control square waves with the different phases are different from each other.

3. The system according to claim 2 , wherein the phases of the control square waves with the different phases are in an arithmetic progression.

4. The system according to claim 1 , further including a status monitor for monitoring status of the multi-core processor and generating status information based on the monitored status, wherein the control square wave is generated based on the status information.

5. The system according to claim 4 , wherein the status monitor includes a temperature monitor for monitoring a temperature of the multi-core processor and generating the status information based on the monitored temperature; and
the pulse width modulation generator is further used for computing a temperature growth rate based on the status information;
wherein, when the temperature growth rate is larger than a threshold, a duty cycle of the control square wave is decreased; when the temperature growth rate is equal to or lower than the threshold, the duty cycle of the control square wave is increased.

6. The system according to the claim 4 , wherein the status monitor includes a load monitor for monitoring a utilization rate of at least one of the multiple processing engines and generating the status information based on the monitored utilization rate;
wherein a duty cycle of the control square wave is adjusted based on the status information, so that a utilization rate of the multi-core processor is kept at a desired value.

7. The system according to the claim 4 , wherein the status monitor includes a temperature monitor and a load monitor;
wherein the temperature monitor is used for monitoring a temperature of the multi-core processor and generating first status information based on the monitored temperature;
the load monitor is used for monitoring a utilization rate of at least one of the multiple processing engines and generating second status information based on the monitored utilization rate; and
the pulse width modulation generator is further used for computing a temperature growth rate based on the first status information;
wherein, when the temperature growth rate is equal to or lower than a threshold, a duty cycle of the control square wave is adjusted based on the second status information, so that a utilization rate of the multi-core processor is kept at a desired value; when the temperature growth rate is larger than the threshold, the duty cycle of the control square wave is decreased.

8. The system according to claim 7 , wherein the load monitor further includes:
an active processing engine counter for monitoring utilization rates of at least two of the multiple processing engines and computing a comprehensive utilization rate of the multi-core processor based on the utilization rates of the at least two of the multiple processing engines;
a utilization rate controller for generating the second status information based on the comprehensive utilization rate.

9. The system according to claim 1 , wherein the multiple processing engines are divided into multiple groups and each of the control square waves with the different phases is respectively used for being input to gatings of processing engines in a corresponding group.

10. The system according to claim 9 , wherein the number of the groups is eight;
and the phase shifter is further used for shifting the phase of the control square wave to generate eight control square waves with phases which are in an arithmetic progression with a 45° common difference, and inputting each of the eight control square waves with the phases which are in the arithmetic progression with the 45° common difference to the gatings of the processing engines in the corresponding group.

11. The system of claim 1 , wherein the phase shifter is configured to:
receive status information including a temperature corresponding to the multicore processor and a utilization growth rate corresponding to the multi-core processor;
adjust phases of the control square waves based on the status information; and
apply the control square waves to the multiple processing engines to control the gatings of each processing engine included in the multi-core processor.

12. A multi-core processor, including:
multiple processing engines, wherein each processing engine includes a gating;
a system for controlling the gating, further including
a pulse width modulation generator for generating a control square wave; and
a phase shifter for shifting a phase of the control square wave to generate control square waves with different phases, and respectively inputting the control square waves with the different phases to control the gating of the each processing engine,

wherein, for each processing engine included in the multiple processing engines, a gating corresponding to the processing engine controls whether the processing engine is enabled or disabled.

13. The multi-core processor according to claim 12 , wherein the phases of the control square waves with the different phases are different from each other.

14. The multi-core processor according to claim 13 , wherein the phases of the control square waves with the different phases are in an arithmetic progression.

15. The multi-core processor according to claim 12 , wherein the system for controlling the gating further includes:
a status monitor for monitoring status of the multi-core processor and generating status information based on the monitored status,
wherein the control square wave is generated based on the status information.

16. The multi-core processor according to claim 15 , wherein the status monitor includes a temperature monitor for monitoring a temperature of the multi-core processor and generating the status information based on the monitored temperature; and
the pulse width modulation generator is further used for computing a temperature growth rate based on the status information;
wherein, when the temperature growth rate is larger than a threshold, a duty cycle of the control square wave is decreased; when the temperature growth rate is equal to or lower than the threshold, the duty cycle of the control square wave is increased.

17. The multi-core processor according to the claim 15 , wherein the status monitor includes a load monitor for monitoring a utilization rate of at least one of the multiple processing engines and generating the status information based on the monitored utilization rate;
wherein a duty cycle of the control square wave is adjusted based on the status information, so that a utilization rate of the multi-core processor is kept at a desired value.

18. The multi-core processor according to the claim 15 , wherein the status monitor includes a temperature monitor and a load monitor;
wherein the temperature monitor is used for monitoring a temperature of the multi-core processor and generating first status information based on the monitored temperature;
the load monitor is used for monitoring a utilization rate of at least one of the mult

Assignees

• Nvidia Corp

Inventors

• Xu Shuang

Classifications

• H03K5/00 Primary

  Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45) · CPC title