Circuit and method to extend a signal comparison voltage range

Patent metadata

Field	Value
Publication number	US-2016248407-A1
Application number	US-201615144929-A
Country	US
Kind code	A1
Filing date	May 3, 2016
Priority date	Mar 12, 2013
Publication date	Aug 25, 2016
Grant date	—

Abstract

A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.

First claim

What is claimed is:

1 . A circuit to extend signal comparison voltage range, the circuit comprising:
a latching circuit; a comparator responsive to a differential pair of input signals, the comparator coupled to the latching circuit and to a node having a dynamic voltage; and a clocked boost circuit coupled to the node and configured to extend a supply voltage range of the comparator via biasing the node, wherein the clocked boost circuit includes:
an inverter coupled between a voltage supply and ground, wherein the inverter is responsive to a clock signal and wherein an output of the inverter is coupled to a first terminal of a capacitor; and
a switch responsive to an inverted clock signal and configured to selectively couple a second terminal of the capacitor to a reference potential.

2 . The circuit of claim 1 , wherein the node provides a supply reference of the comparator.

3 . The circuit of claim 2 , wherein the comparator comprises:
a first transistor coupled to the node and responsive to a first input signal; and a second transistor coupled to the node and responsive to a second input signal, wherein an output of the comparator indicates whether a first charge rate through the first transistor to the supply reference exceeds a second charge rate through the second transistor to the supply reference.

4 . An apparatus to boost a common mode voltage of a differential signal pair, the apparatus comprising:
a dynamic latched comparator including:
a first transistor coupled to receive a first input signal of the differential signal pair, wherein a source of the first transistor is coupled to a node having a dynamic voltage; and
a second transistor coupled to receive a second input signal of the differential signal pair, wherein a source of the second transistor is coupled to the node; and
a clocked boost circuit including a capacitor coupled to the node, wherein the capacitor is selectively charged in response to a clock signal, wherein the capacitor selectively biases the node to boost the common mode voltage, and wherein the clocked boost circuit includes:
an inverter coupled between a voltage supply and ground, wherein the inverter is responsive to a clock signal and wherein an output of the inverter is coupled to a first terminal of the capacitor; and

a switch responsive to an inverted clock signal and configured to selectively couple a second terminal of the capacitor to a reference potential.

5 . The apparatus of claim 4 , wherein the first transistor and the second transistor are p-type metal oxide semiconductor (PMOS) transistors, and wherein boosting the common mode voltage includes biasing the node to a voltage greater than a supply voltage.

6 . The circuit of claim 5 , wherein the clocked boost circuit includes:
an inverter coupled between a voltage supply and ground, wherein the inverter is responsive to a clock signal and wherein an output of the inverter is coupled to the first terminal of the capacitor; and a switch responsive to an inverted clock signal and configured to selectively couple a second terminal of the capacitor to the supply voltage.

Assignees

• Qualcomm Inc

Inventors

• Goldblatt Jeremy

Classifications

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K5/2481

  with at least one differential stage · CPC title

• H03K3/35613 Primary

  the input circuit having a differential configuration · CPC title

• H03K5/249

  using clock signals · CPC title

• H03K5/00 Primary

  Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45) · CPC title