Semiconductor device with channelstopper and method for producing the same

Patent metadata

Field	Value
Publication number	US-10038052-B2
Application number	US-201615085618-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	Mar 31, 2015
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A vertical semiconductor device comprises a substrate having a front surface and a back surface, an active area (AA) located in the substrate, having a drift region doped with a first dopant type, an edge termination region (ER) laterally surrounding the active area (AA), a channelstopper terminal provided at the front surface and located in the edge termination region (ER), and a first suppression trench located on a side of the channelstopper terminal towards the active region (AA), and provided adjacent to the channelstopper terminal. Further, a production method for such a semiconductor device is provided.

First claim

The invention claimed is:

1. A vertical semiconductor device comprising:
a substrate having a front surface and a back surface,
an active area located in the substrate;
an edge termination region laterally surrounding the active area,
a drift region extending from within the active area to within the edge termination region, the drift region doped with a first dopant type;
a body region located in the active area on and in contact with the drift region, and doped with a second dopant type opposite the first dopant type;
a channelstopper terminal provided on the front surface and located in the edge termination region, wherein the channelstopper terminal is doped with the second dopant type, and is separated from the body region by the drift region; and
a first suppression trench located on a side of the channelstopper terminal towards the active area, wherein a first side of the first suppression trench facing the active area is in contact with the drift region, and a second side of the first suppression trench opposite the active area is in contact with the channelstopper terminal.

2. The vertical semiconductor device of claim 1 , wherein the drift region has a vertically inhomogeneous doping profile with a lower doping towards the front surface of the substrate.

3. The vertical semiconductor device of claim 1 , wherein a depth of the first suppression trench is from about 2 to about 7 μm, and a width of the first suppression trench is from about 0.5 to about 3 μm.

4. The vertical semiconductor device of claim 1 , wherein walls of the first suppression trench are covered with a layer comprising at least one of: silicon oxide, and doped silicon oxide, and wherein the first suppression trench comprises at least one of:
polysilicon,
silicon oxide,
a high-k-material, and
phosphorus silicate glass.

5. The vertical semiconductor device of claim 1 , wherein
the first dopant type is an n-dopant, and the second dopant type is a p-dopant, or
the first dopant type is a p-dopant, and the second dopant type is an n-dopant.

6. The vertical semiconductor device of claim 1 , wherein the device is one of a diode, an IGBT, and a Power MOSFET.

7. The vertical semiconductor device of claim 1 , further comprising an outer suppression trench provided between the channelstopper terminal and a substrate edge of the substrate.

8. The vertical semiconductor device of claim 1 , wherein the first suppression trench has a filling comprising phosphorus silicate glass.

9. The vertical semiconductor device of claim 1 , and further comprising a field stop region disposed below the drift region.

10. The vertical semiconductor device of claim 1 , wherein, the channelstopper terminal has p-type doping.

11. The vertical semiconductor device of claim 1 , further comprising a drain region in contact with the drift region, wherein the drain region is doped with the first dopant type, the drain region is separated from the body region by the drift region, and the drain region is electrically connected to the channelstopper terminal via an ohmic contact to the channelstopper terminal.

12. The vertical semiconductor device of claim 1 , wherein the drift region has a vertically inhomogeneous doping profile.

13. The vertical semiconductor device of claim 12 , wherein the vertically inhomogeneous doping profile is formed by ion implantation.

14. The vertical semiconductor device of claim 1 , wherein walls of the first suppression trench are covered with a dielectric layer.

15. A method for producing a vertical semiconductor device, comprising:
providing a substrate having a front surface and a back surface,
providing an active area located in the substrate,
providing an edge termination region laterally surrounding the active area,
providing a drift region extending from within the active area to within the edge termination region, the drift region doped with a first dopant type;
providing a body region located in the active area on and in contact with the drift region, and doped with a second dopant type opposite the first dopant type;
providing a channelstopper terminal provided on the front surface and located in the edge termination region, wherein the channelstopper terminal is doped with the second dopant type, and is separated from the body region by the drift region; and
providing a first suppression trench located on a side of the channelstopper terminal towards the active area, wherein a first side of the first suppression trench facing the active area is in contact with the drift region, and a second side of the first suppression trench opposite the active area is in contact with the channelstopper terminal.

16. The method of claim 15 , wherein the substrate has a vertically inhomogeneous doping profile, preferably with a lower doping towards the front surface of the substrate.

17. The method of claim 16 , wherein the vertically inhomogeneous doping profile is achieved by an implantation of protons.

18. The method of claim 15 , further comprising: covering walls of the first suppression trench with at least one of: a layer of silicon oxide, and a thin layer of doped silicon oxide, and filling the first suppression trench with at least one of:
polysilicon, and
silicon oxide, and
a high-k-material, and
phosphorus silicate glass.

19. The method of claim 15 , wherein a filling of the first suppression trench is heavily doped with a dopant the first dopant type, by employing a phosphorus silicate glass filling of the first suppression trench.

20. The method of claim 15 , wherein the first suppression trench is produced in the same production step as a gate trench of the active area.

21. The method of claim 15 , wherein a further suppression trench is provided between the channelstopper terminal and the active area.

22. The method of claim 15 , wherein an outer suppression trench is provided between the channelstopper terminal and a substrate edge of the substrate, which is heavily doped with a first dopant of the first dopant type, and which is doped by at least one of: diffusion, implantation, preferably by diffusion of P atoms from phosphorus silicate glass.

23. The method of claim 15 , wherein the doping of the first suppression trench and/or the further suppression trench is produced by diffusing or implanting a dopant into the region of the respective trench and optionally into adjacent areas.

Assignees

• Infineon Technologies Ag

Inventors

• Falck Elmar
• Pfirsch Frank Dieter
• Schulze Hans-Joachim
• Voss Stephan

Classifications

• H10W10/031 Primary

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H01L29/7813

  Electricity · mapped topic

• H01L21/761

  Electricity · mapped topic