Semiconductor device package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10037974-B2
Application number	US-201715416907-A
Country	US
Kind code	B2
Filing date	Jan 26, 2017
Priority date	Mar 8, 2016
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate.

First claim

What is claimed is:

1. A semiconductor device package, comprising: a package substrate comprising a first surface, a second surface opposite to the first surface, and an edge; a first electronic device positioned over and electrically connected to the package substrate through the first surface; a second electronic device positioned over and electrically connected to the first electronic device; and a first molding layer positioned over the package substrate, wherein the first molding layer: encapsulates a portion of the first surface of the package substrate; and comprises a portion extending from the first surface of the package substrate to the second surface of the package substrate and covering the edge of the package substrate, wherein a thickness of the portion of the first molding layer measured in a direction parallel to the edge of the package substrate is substantially equal to a total thickness of the package substrate measured in the direction, and the first molding layer is further located between the first electronic device and the second electronic device.

2. The semiconductor device package of claim 1 , wherein the first electronic device comprises a plurality of through vias, and the second electronic device is electrically connected to the package substrate through the plurality of through vias of the first electronic device.

3. The semiconductor device package of claim 1 , further comprising:
a plurality of first conductive structures positioned between and electrically connected to the package substrate and the first electronic device; and
a plurality of second conductive structures positioned between and electrically connected to the first electronic device and the second electronic device.

4. The semiconductor device package of claim 1 , wherein the first molding layer further encapsulates a portion of the first electronic device, and a portion of the second electronic device.

5. The semiconductor device package of claim 1 , further comprising a first underfill layer positioned between the package substrate and the first electronic device.

6. The semiconductor device package of claim 1 , further comprising a second underfill layer positioned between the first electronic device and the second electronic device.

7. The semiconductor device package of claim 1 , wherein the first molding layer is further located between the package substrate and the first electronic device.

8. The semiconductor device package of claim 1 , further comprising a second molding layer comprising a sidewall, positioned over the first electronic device, wherein the second molding layer encapsulates a portion of the first electronic device and a portion of the second electronic device, and the sidewall of the second molding layer is surrounded by the first molding layer.

9. The semiconductor device package of claim 1 , further comprising a plurality of conductors positioned over and electrically connected to the second surface of the package substrate.

10. The semiconductor device package of claim 1 , wherein the first molding layer exposes an upper surface of the second electronic device, and the semiconductor device package further comprises a heat spreader positioned over the upper surface of the second electronic device.

11. A semiconductor device package, comprising: a package substrate comprising a first surface, a second surface opposite to the first surface, and an edge; a first electronic device positioned over and electrically connected to the package substrate through the first surface; a second electronic device positioned over and electrically connected to the first electronic device; and a first molding layer positioned over the package substrate, wherein the first molding layer: encapsulates a portion of the first surface of the package substrate; and comprises a portion extending from the first surface of the package substrate to the second surface of the package substrate and covering the edge of the package substrate, wherein a thickness of the portion of the first molding layer measured in a direction parallel to the edge of the package substrate is substantially equal to a total thickness of the package substrate measured in the direction parallel to the edge of the package substrate; and wherein a warpage of the semiconductor device package is less than 8 mils.

12. The semiconductor device package of claim 11 , wherein the first molding layer has a thickness in the direction parallel to the edge of the package substrate measured from the first surface of the package substrate to an upper surface of the first molding layer, and a ratio of the thickness of the first molding layer to the thickness of the package substrate is less than or equal to 0.7.

13. The semiconductor device package of claim 11 , wherein a coefficient of thermal expansion (CTE) of the first molding layer is in a range from 5 to 50 ppm/° C.

14. The semiconductor device package of claim 11 , further comprising a second molding layer comprising a sidewall, positioned over the first electronic device, wherein the second molding layer encapsulates a portion of an upper surface of the first electronic device and a portion of an upper surface and a sidewall of the second electronic device, and the sidewall of the second molding layer is surrounded by the first molding layer.

15. The semiconductor device package of claim 14 , wherein a coefficient of thermal expansion (CTE) of the second molding layer is in a range from 5 to 50 ppm/° C.

16. A semiconductor device package, comprising: a package substrate comprising a first surface, and a second surface opposite to the first surface; a first electronic device comprising an upper surface and a sidewall, and positioned over and electrically connected to the package substrate through the first surface; a second electronic device comprising a sidewall and positioned over and electrically connected to the first electronic device; a first molding layer positioned over the package substrate, wherein the first molding layer encapsulates a portion of the first surface of the package substrate; and a second molding layer comprising a sidewall, positioned over the first electronic device, wherein the second molding layer encapsulates a portion of the upper surface of the first electronic device and the sidewall of the second electronic device, wherein the sidewall of the second molding layer is surrounded by, and in contact with, the first molding layer, and the sidewall of the first electronic device is exposed from the second molding layer.

17. The semiconductor device package of claim 16 , wherein the second electronic device comprises an upper surface and the second molding layer further encapsulates the upper surface of the second electronic device.

18. The semiconductor device package of claim 16 , wherein the second electronic device comprises an upper surface, and the semiconductor device package further comprises a heat spreader positioned over the upper surface of the second electronic device.

19. The semiconductor device package of claim 16 , wherein the first molding layer comprises an upper surface, the second molding layer comprises an upper surface, and the upper surface of the second molding layer is substantially coplanar with the upper surface of the first molding layer.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chang Chien Chien Lin
• Lee Chang Chi
• Kao Chin-Li
• Chen Dao-Long
• Cheng Ta-Chien

Classifications

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title