Wafer-level package having asynchronous FIFO buffer used to deal with data transfer between different dies and associated method

Patent metadata

Field	Value
Publication number	US-10037293-B2
Application number	US-201615015145-A
Country	US
Kind code	B2
Filing date	Feb 4, 2016
Priority date	Feb 17, 2015
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.

First claim

What is claimed is:

1. A wafer-level package comprising:
a first die, comprising:
a first clock source, arranged to generate a first clock; and
a first sub-system, arranged to generate transmit data; and
an output circuit, arranged to output the transmit data according to the first clock; and

a second die, comprising:
a second sub-system;
a second clock source, arranged to generate a second clock; and

an input circuit, comprising an asynchronous first-in first-out (FIFO) buffer, wherein the input circuit is arranged to refer to the first clock to buffer the transmit data transferred from the output circuit in the asynchronous FIFO buffer, and refer to the second clock to output the buffered transmit data in the asynchronous FIFO buffer to the second sub-system;
wherein the first die and the second die are wafer-level packaged.

2. The wafer-level package of claim 1 , wherein the first die is identical to the second die.

3. The wafer-level package of claim 1 , wherein the first die and the second die are assembled in the wafer-level package to perform a network switch function.

4. The wafer-level package of claim 1 , wherein the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package.

5. The wafer-level package of claim 1 , wherein the first sub-system is further arranged to employ a flow control scheme to manage an input data flow of the asynchronous FIFO buffer.

6. The wafer-level package of claim 5 , wherein the flow control scheme enables a wait state of the first sub-system, regardless of a use status of the asynchronous FIFO buffer.

7. The wafer-level package of claim 6 , wherein the flow control scheme ensures that a maximum continuous active interface valid duration does not exceed a predetermined threshold.

8. The wafer-level package of claim 1 , wherein the input circuit is further arranged to employ a flow control scheme to manage an input data flow of the asynchronous FIFO buffer.

9. The wafer-level package of claim 8 , wherein the flow control scheme generates a stall event to the first sub-system in response to a use status of the asynchronous FIFO buffer.

10. The wafer-level package of claim 9 , wherein the flow control scheme generates the stall event when detecting that a size of a used storage space in the asynchronous FIFO buffer reaches a predetermined threshold.

11. A method for managing data transfer between a first die and a second die in a wafer-level package, comprising:
generating a first clock from a first clock source;
generating transmit data from a first sub-system in the first die;
outputting the transmit data via an output circuit of the first die according to the first clock;
generating a second clock from a second clock source;
referring to the first clock for buffering the transmit data transferred from the output circuit in an asynchronous first-in first-out (FIFO) buffer in an input circuit of the second die; and
referring to the second clock for outputting the buffered transmit data in the asynchronous FIFO buffer to a second sub-system in the second die;
wherein the first die and the second die are wafer-level packaged.

12. The method of claim 11 , wherein the first die is identical to the second die.

13. The method of claim 11 , wherein the first die and the second die are assembled in the wafer-level package to perform a network switch function.

14. The method of claim 11 , wherein the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package.

15. The method of claim 11 , further comprising:
managing an input data flow of the asynchronous FIFO buffer according to a flow control scheme employed by the first sub-system.

16. The method of claim 15 , wherein the flow control scheme enables a wait state of the first sub-system, regardless of a use status of the asynchronous FIFO buffer.

17. The method of claim 16 , wherein the flow control scheme ensures that a maximum continuous active interface valid duration does not exceed a predetermined threshold.

18. The method of claim 11 , further comprising:
managing an input data flow of the asynchronous FIFO buffer according to a flow control scheme employed by the input circuit.

19. The method of claim 18 , wherein the flow control scheme generates a stall event to the first sub-system in response to a use status of the asynchronous FIFO buffer.

Assignees

• Mediatek Inc
• Nephos Hefei Co Ltd

Inventors

• Chen Yi-Hung
• Liu Yuan-Chin

Classifications

• H04L7/005

  Correction by an elastic buffer · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• G06F13/362 Primary

  with centralised access control · CPC title

• H04L7/00

  Arrangements for synchronising receiver with transmitter {(synchronisation of generators of electric oscillations or pulses H03L7/00)} · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title