Display panel and a manufacturing method thereof, a TFT test method

Patent metadata

Field	Value
Publication number	US-10036906-B2
Application number	US-201615322549-A
Country	US
Kind code	B2
Filing date	Apr 15, 2016
Priority date	Jun 8, 2015
Publication date	Jul 31, 2018
Grant date	Jul 31, 2018

Abstract

A display panel which includes a display area and a peripheral area around the display area is provided. The peripheral area includes an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines. The electroluminescent layer test region includes a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers. The TFT test region includes a plurality of thin film transistors. Each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.

First claim

The invention claimed is:

1. A display panel, comprising a display area and a peripheral area around the display area, wherein the peripheral area comprises: an electroluminescent layer test region, a TFT test region and a plurality of lead-out lines; wherein,
the electroluminescent layer test region comprises a plurality of thin film transistors having electroluminescent layers, a first test line connecting sources of the plurality of thin film transistors having electroluminescent layers, and a switch lead and a second test line connecting gates of the plurality of thin film transistors having electroluminescent layers;
the TFT test region comprises a plurality of thin film transistors;
each of the plurality of lead-out lines is used for connecting a source-drain metal layer of one thin film transistor in the electroluminescent layer test region and a source-drain metal layer of one thin film transistor in the TFT test region.

2. The display panel according to claim 1 , wherein the thin film transistors having electroluminescent layers in the electroluminescent layer test region are in one-to-one correspondence with the thin film transistors in the TFT test region.

3. The display panel according to claim 1 , wherein the thin film transistors having electroluminescent layers in the electroluminescent layer test region comprise successively from down to up: a substrate, a buffer layer, a low temperature polysilicon, a gate insulating layer, a gate, an interlayer insulating layer, a source-drain metal electrode, a flat layer, a pixel definition layer and an electroluminescent layer;
wherein the material of the thin film transistors having electroluminescent layers is the same as the material of the thin film transistors in the display area.

4. The display panel according to claim 1 , wherein the thin film transistors in the TFT test region comprises successively from down to up: a buffer layer, a gate insulating layer, a gate, an interlayer insulating layer, a source-drain metal electrode, a flat layer and a pixel definition layer;
wherein the material of the thin film transistors in the TFT test region is the same as the material of the thin film transistors in the display area.

5. A method for testing characteristics of TFT using the display panel as claimed in claim 1 , wherein the method comprises:
applying a first voltage to the switch lead, such that the thin film transistors in the electroluminescent layer test region are turned on, the thin film transistors in the TFT test region are turned on, and the electroluminescent layer emits light;
applying a second voltage to the switch lead, such that the thin film transistors in the electroluminescent layer test region are cut off, and the thin film transistors in the TFT test region are turned on, measuring electrical characteristics of the thin film transistors in the TFT test region;
wherein the first voltage is a voltage that turns on the thin film transistors, the second voltage is a voltage that cuts off the thin film transistors.

6. The method for testing characteristics of TFT according to claim 5 , wherein measuring electrical characteristics of the thin film transistors in the TFT test region comprises:
calculating short range uniformity of the thin film transistors in the TFT test region based on a plurality of data, wherein each data is obtained from the following way:
fixing a first probe on the first test line of the electroluminescent layer test region, fixing a second probe on the second test line of the electroluminescent layer test region, placing a third probe in the TFT test region, and moving the third probe within the TFT test region, one data being obtained every time the third probe is moved.

7. A manufacturing method of the display panel as claimed in claim 1 , characterized by comprising: manufacturing the peripheral area around the display area while manufacturing the display area, wherein,
a switch lead and a second test line are formed when gates of thin film transistors having electroluminescent layers are formed;
a first test line is formed when sources of thin film transistors having electroluminescent layers are formed;
a plurality of lead-out lines are formed when source-drain metal layers of thin film transistors having electroluminescent layers and source-drain metal layers of thin film transistors in the TFT test region are formed.

8. The manufacturing method of the display panel according to claim 7 , wherein forming thin film transistors having electroluminescent layers in the electroluminescent test region comprises:
forming a buffer layer, a low temperature polysilicon, a gate insulating layer, a gate, an interlayer insulating layer, a source-drain metal electrode, a flat layer, a pixel definition layer and an electroluminescent layer successively on an array substrate of the electroluminescent layer test region of the peripheral area.

9. The manufacturing method of the display panel according to claim 7 , wherein forming thin film transistors in the TFT test region comprises:
forming a buffer layer, a gate insulating layer, a gate, an interlayer insulating layer, a source-drain metal electrode, a flat layer and a pixel definition layer successively on an array substrate of the TFT test region of the peripheral area.

10. The method for testing characteristics of TFT according to claim 5 , wherein the thin film transistors having electroluminescent layers in the electroluminescent layer test region are in one-to-one correspondence with the thin film transistors in the TFT test region.

11. The method for testing characteristics of TFT according to claim 5 , wherein the thin film transistors having electroluminescent layers in the electroluminescent layer test region comprise successively from down to up: a substrate, a buffer layer, a low temperature polysilicon, a gate insulating layer, a gate, an interlayer insulating layer, a source-drain metal electrode, a flat layer, a pixel definition layer and an electroluminescent layer;
wherein the material of the thin film transistors having electroluminescent layers is the same as the material of the thin film transistors in the display area.

12. The method for testing characteristics of TFT according to claim 5 , wherein the thin film transistors in the TFT test region comprises successively from down to up:
a buffer layer, a gate insulating layer, a gate, an interlayer insulating layer, a source-drain metal electrode, a flat layer and a pixel definition layer;
wherein the material of the thin film transistors in the TFT test region is the same as the material of the thin film transistors in the display area.

13. The manufacturing method of the display panel according to claim 7 , wherein the thin film transistors having electroluminescent layers in the electroluminescent layer test region are in one-to-one correspondence with the thin film transistors in the TFT test region.

14. The manufacturing method of the display panel according to claim 7 , wherein the thin film transistors having electroluminescent layers in the electroluminescent layer test region comprise successively from down to up: a substrate, a buffer layer, a low temperature polysilicon, a gate insulating layer, a gate, an interlayer insulating layer, a source-drain metal electrode, a flat layer, a pixel definition layer and an electroluminescent layer;
wherein the material of the thin film transistors having electroluminescent layers is the same as the material of the thin film transistors in the display area.

15. The manufacturing method of the display panel according to claim 7 , wherein the thi

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Zuqiang
• Li Guang
• Sun Liang
• Lu Xiaoyong

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G02F1/1309 Primary

  Repairing; Testing · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• H01L27/3262

  Electricity · mapped topic

• G02F2001/136295

  Physics · mapped topic