Integrated circuit for saturation detection, wireless device and method of detecting saturation

Patent metadata

Field	Value
Publication number	US-10033367-B2
Application number	US-201514702809-A
Country	US
Kind code	B2
Filing date	May 4, 2015
Priority date	Dec 2, 2014
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.

First claim

The invention claimed is:

1. An integrated circuit for saturation detection, the integrated circuit comprising:
a plurality of gain components;
a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components;
a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors, wherein the plurality of logic elements comprises a plurality of logic AND gates, wherein an output from each of the logic AND gates is operably coupled to a respective register bit to store the logic AND gate output; and
a controller operably coupled to the plurality of logic AND gates, wherein the controller is arranged to apply a signal to a second input of individual ones of the plurality of logic AND gates such that an output of the respective logic AND gate identifies a saturation event of the saturation detector associated with that respective logic AND gate, and wherein the controller is arranged to receive a trigger to initiate a polling operation of the register bits to identify the individual saturation detector that is subject to the saturation event.

2. The integrated circuit of claim 1 wherein an output from each of the plurality of saturation detectors is coupled to at least one logic gate such that an output from the logic gate identifies that a saturation event has occurred in at least one of the plurality of saturation detectors.

3. The integrated circuit of claim 2 further comprising a single output of the integrated circuit operably coupled to a plurality of logic gates wherein the single output is arranged to identify a respective gain component of the plurality of gain components that is exhibiting a saturation event.

4. The integrated circuit of claim 2 wherein the at least one logic gate is at least one logic OR gate.

5. The integrated circuit of claim 1 wherein a gain component coupled to the individual saturation detector that is subject to the saturation event is arranged to receive a signal to control an adjustment of a gain applied to signals passing there through.

6. The integrated circuit of claim 1 wherein the controller sequentially outputs a logic ‘1’ to an input of each logic AND gate in turn to initiate the polling operation of the register bits.

7. The integrated circuit of claim 6 wherein the controller identifies the individual saturation detector that is subject to a saturation event controller by identifying a logic ‘1’ value in a respective register bit when applying a logic ‘1’ to the logic AND gate input.

8. An integrated circuit for saturation detection, the integrated circuit comprising:
a plurality of gain components;
a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components;
a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors, wherein the plurality of logic elements comprises a plurality of logic AND gates, wherein an output from each of the logic AND gates is operably coupled to a respective register bit to store the logic AND gate output; and
a controller operably coupled to the plurality of logic AND gates, wherein the controller is arranged to apply a signal to a second input of individual ones of the plurality of logic AND gates such that an output of the respective logic AND gate identifies a saturation event of the saturation detector associated with that respective logic AND gate, and wherein each respective register bit is accessible by an interface port of the integrated circuit to enable external access to the respective register bit thereby identifying the respective gain component that is subject to a saturation event.

9. An integrated circuit for saturation detection, the integrated circuit comprising:
a plurality of gain components;
a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components;

a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors, wherein the plurality of logic elements comprises a plurality of digital flip flops, wherein an output from each of the digital flip flops is operably coupled to a respective register bit to store the digital flip flop output; and
a controller operably coupled to the plurality of digital flip flops, wherein the controller is arranged to apply a signal to a second input of individual ones of the plurality of digital flip flops such that an output of the respective digital flip flop identifies a saturation event of the saturation detector associated with that respective digital flip flop, and wherein the controller selectively applies a store control signal to a further input of a number of the digital flip flops to freeze the output stored in the register bit.

10. The integrated circuit of claim 1 further comprising sense logic operably coupled to the output of the plurality of saturation detectors and arranged to determine a number of saturation events.

11. The integrated circuit of claim 10 wherein the sense logic outputs a flag to the controller or an external port if the determined number of saturation events is above a pre-set threshold.

12. An integrated circuit for saturation detection, the integrated circuit comprising:
a plurality of gain components;
a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components;
a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors, wherein the plurality of logic elements comprises a plurality of digital flip flops, wherein an output from each of the digital flip flops is operably coupled to a respective register bit to store the digital flip flop output; and
a controller operably coupled to the plurality of digital flip flops, wherein the controller is arranged to apply a signal to a second input of individual ones of the plurality of digital flip flops such that an output of the respective digital flip flop identifies a saturation event of the saturation detector associated with that respective digital flip flop, and wherein each respective register bit is accessible by an interface port of the integrated circuit to enable external access to the respective register bit thereby identifying the respective gain component that is subject to a saturation event.

13. A radar device comprising:
a plurality of gain components;
a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components;
a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors, wherein the plurality of logic elements comprises a plurality of logic AND gates, wherein an output from each of the logic AND gates is operably coupled to a respective register bit to store the logic AND gate output; and
a controller operably coupled to the plurality of logic AND gates, wherein the controller is arranged to apply a signal to a second input of individual ones of the plurality of logic AND gates such that an output of the respective logic AND gate identifies a saturation event of the saturation detector associated with that respective logic AND gate, and wherein the controller is arranged to receive a trigger to initiate a polling operation of the register bits to identify the individual saturation detector that is subject to the saturation event.

Assignees

• Pavao Moreira Cristian
• Delbecq Dominique
• Goumballa Birama
• Salle Didier
• Nxp Usa Inc

Inventors

• Pavao-Moreira Cristian
• Delbecq Dominique
• Goumballa Birama
• Salle Didier

Classifications

• G01S7/4021

  of receivers · CPC title

• G01S7/032

  Constructional details for solid-state radar subsystems · CPC title

• H03K5/19 Primary

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title

• G01S13/345

  using triangular modulation · CPC title

• G01S7/354

  Extracting wanted echo-signals (Doppler systems G01S13/50) · CPC title