Latched comparator circuit

Patent metadata

Field	Value
Publication number	US-10033360-B2
Application number	US-201615372958-A
Country	US
Kind code	B2
Filing date	Dec 8, 2016
Priority date	Jun 24, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Some embodiments include apparatuses having input nodes to receive input signals, output nodes to provide output signals, a first stage including a first pair of input transistors, the first pair of transistors including gates coupled to the input nodes, a second stage including a second pair of input transistors, the second pair of transistors including gates coupled to the input nodes, and a third stage including inverters coupled to the output nodes. The inverters are coupled to the first and second stages at the same nodes to switch the output signals between different voltages based on the input signals.

First claim

What is claimed is:

1. An apparatus comprising:
input nodes included in a first device to receive input data signals from a second device;
output nodes included in the first device to provide output data signals;
a first stage included in the first device, the first stage including a first pair of input transistors, the first pair of input transistors including gates coupled to the input nodes;
a second stage included in the first device, the second stage including a second pair of input transistors, the second pair of input transistors including gates coupled to the input nodes; and
a third stage included in the first device, the third stage including inverters coupled to the output nodes, the inverters coupled to the first and second stages at same nodes to switch the output data signals between different voltages based on the input data signals, wherein the second stage is configured to assist the first stage to sample the input data signals when a value of one of the input data signals is greater than a value of an operating voltage of the third stage.

2. The apparatus of claim 1 , wherein the first device includes a circuit coupled to the output nodes to provide first and second additional output data signals based on the output data signals.

3. The apparatus of claim 2 , wherein the circuit includes a first logic gate and a second logic gate, the first logic gate including a first input coupled to a first output node of the output nodes, a second input coupled to an output of the second logic gate, and an output coupled to a first input of the second logic gate, the second logic gate including a second input coupled to a second output node of the output nodes.

4. The apparatus of claim 1 , wherein the second stage is to receive a signal to deactivate the second stage.

5. The apparatus of claim 1 , wherein the first device is included in a first die separated from the second device.

6. An apparatus comprising:
a first node included in a first device to receive a first input data signal from a second device;
a second node included in the first device to receive a second input data signal generated by the first device;
output nodes included in the first device to provide output data signals;
a first stage included in the first device, the first stage including a first pair of input transistors, the first pair of input transistors including gates coupled to the first and second nodes;
a second stage included in the first device, the second stage including a second pair of input transistors, the second pair of input transistors including gates coupled to the first and second nodes; and
a third stage included in the first device, the third stage including inverters coupled to the output nodes, the inverters coupled to the first and second stages at same nodes to switch the output data signals between different voltages based on the first and second input data signals, wherein the first, second, and third stages are included in a receiver of the first device, and the first node is to receive the first input data signal from a transmitter included in the second device.

7. An apparatus comprising:
a first node included in a first device to receive a first input data signal from a second device;
a second node included in the first device to receive a second input data signal generated by the first device;
output nodes included in the first device to provide output data signals;
a first stage included in the first device, the first stage including a first pair of input transistors the first pair of input transistors including gates coupled to the first and second nodes;
a second stage included in the first device, the second stage including a second pair of input transistors, the second pair of input transistors including gates coupled to the first and second nodes; and
a third stage included in the first device, the third stage including inverters coupled to the output nodes, the inverters coupled to the first and second stages at same nodes to switch the output data signals between different voltages based on the first and second input data signals, wherein:
the inverters include a first inverter and a second inverter;
the first inverter includes a first plurality of transistors coupled between a first supply node and a second supply node, the first plurality of transistors including a first transistor and a second transistor coupled between a first output node of the output nodes and the second supply node; and
the second inverter includes a second plurality of transistors coupled between the first and second supply nodes, the second plurality of transistors including a third transistor and a fourth transistor coupled between a second output node of the output nodes and the second supply node.

8. The apparatus of claim 7 , wherein the first and second transistors of the first plurality of transistors and the third and fourth transistors of the second plurality of transistors have a same transistor type.

9. The apparatus of claim 7 , wherein the same nodes includes a node between the first and second transistors and a node between the third and fourth transistors.

10. The apparatus of claim 9 , wherein:
one transistor of the first pair of input transistor is coupled between the second supply node and the node between the first and second transistors; and
one transistor of second pair of input transistors includes is coupled between the second supply node and the node between the third and fourth transistors.

11. The apparatus of claim 10 , wherein the third stage includes:
a third input transistor coupled between the first and second supply nodes, the third input transistor including a gate coupled to the first node; and
a fourth input transistor coupled between the first and second supply nodes, the fourth input transistor including a gate coupled to the second node.

12. The apparatus of claim 11 , wherein the first and second input transistors have a first transistor type and the third and fourth input transistors have a second transistor type.

13. The apparatus of claim 12 , wherein the first transistor type includes n-type and the second transistor type includes p-type.

14. The apparatus of claim 12 , wherein the firs transistor type includes p-type and the second transistor type includes n-type.

15. An apparatus comprising:
conductive paths on a circuit board;
an antenna coupled to the conductive path;
a first device coupled to the conductive path; and
a second device coupled to the conductive path, the second device including:
input nodes to receive input data signals from the first device;
output nodes to provide output data signals;
a first stage including a first pair of input transistors, the first pair of input transistors including gates coupled to the input nodes;
a second stage including a second pair of input transistors, the second pair of input transistors including gates coupled to the input nodes; and
a third stage including inverters coupled to the output nodes, the inverters coupled to the first and second stages at same nodes to switch the output data signals between different voltages based on the input data signals, wherein the input nodes are part of one of a solder balls, solder bumps, and pins wherein the first, second, and third stages are included in a receiver of the second device, and the input nodes are to receive the input data signal from a transmitter included in the first device.

16. The apparatus of claim 15 , wherein one of the first and second devices includes a processor.

17. The apparatus of claim 15

Assignees

• Intel Corp

Inventors

• Aw Chee Hong

Classifications

• H03K3/356113 Primary

  using additional transistors in the input circuit · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K5/249

  using clock signals · CPC title

• H03K5/2481

  with at least one differential stage · CPC title

• H03K3/356191

  with synchronous operation · CPC title