High-frequency semiconductor amplifier circuit

Patent metadata

Field	Value
Publication number	US-10033332-B2
Application number	US-201715444242-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Sep 5, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.

First claim

What is claimed is:

1. A high-frequency semiconductor amplifier circuit, comprising:
a first input terminal at which a first signal having a high frequency can be input;
a first output terminal at which an output signal corresponding to the first signal can be output;
a first transistor on a silicon on insulator (SOI) substrate, a gate of the first transistor being connected to the first input terminal via a first capacitor;
a second transistor on the SOI substrate and connected between a source of the first transistor and a reference potential terminal;
a third transistor on the SOI substrate and having a source connected to a drain of the first transistor and a drain connected to the first output terminal via a second capacitor; and
a bias generation circuit having an first input control signal terminal at which a first input control signal can be received, a first bias voltage terminal connected to the gate of the first transistor via a first resistor, a second bias voltage terminal connected to a gate of the third transistor via a second resistor, and a first voltage terminal connected to the drain of the third transistor via a third resistor and a first inductor connected in parallel and to a gate of the second transistor via a fourth resistor, wherein the bias generation circuit is configured to supply:
a first voltage at the first voltage terminal to place the second transistor in a conducting state when the first input control signal is at a first level, and to place the second transistor in a non-conducting state when the first input control signal is at a second level;
a first bias voltage at the first bias terminal at a first bias level when the first input control single is at the first level and at a second bias level that is higher than the first bias level when the first input control signal is at the second level; and
a first voltage at the first voltage terminal at a first intermediate level that is between a reference potential and a power supply potential supplied to the bias generation circuit when the first input control signal is at the first level, and at the reference potential when the first input control signal is at the second level.

2. The high-frequency semiconductor amplifier circuit according to claim 1 , further comprising:
a third capacitor having a first end connected to a gate of the third transistor; and
a first switching circuit connected between the reference potential terminal and a second end of the third capacitor, the first switching circuit being configured to electrically connect the second end of the third capacitor to the reference potential terminal when the first input control signal is at the first level and to electrically disconnect the second end of the third capacitor to the reference potential terminal when the first input control signal is at the second level.

3. The high-frequency semiconductor amplifier circuit according to claim 1 , further comprising:
a second inductor connected between the second transistor and the reference potential terminal.

4. The high-frequency semiconductor amplifier circuit according to claim 1 , further comprising:
a second inductor connected between the second transistor and the source of the first transistor.

5. The high-frequency semiconductor amplifier circuit according to claim 1 , further comprising:
a capacitance adjustment circuit connected in parallel with the second capacitor between the drain of the third transistor and the first output terminal and including a fourth transistor and a fourth capacitor connected in series, a gate of the fourth transistor being connected to the bias generation circuit that supplies a gate voltage to the gate of the fourth transistor according to the level of the first input control signal.

6. The high-frequency semiconductor amplifier circuit according to claim 1 , further comprising:
a third capacitor having a first end connected to a gate of the third transistor;
a first switching circuit connected between the reference potential terminal and a second end of the third capacitor, the first switching circuit being configured to electrically connect the second end of the third capacitor to the reference potential terminal when the first input control signal is at the first level and to electrically disconnect the second end of the third capacitor to the reference potential terminal when the first input control signal is at the second level;
a first electrostatic protection circuit connected between a source of the first switching circuit and a power supply ground terminal connected to the bias generation circuit; and
a second electrostatic protection circuit connected between the source of the first transistor and the power supply ground terminal.

7. The high-frequency semiconductor amplifier circuit according to claim 1 , further comprising:
a first p-channel metal oxide semiconductor (PMOS) transistor connected between the first voltage terminal and the third resistor, a gate of the first PMOS transistor being grounded; and
a capacitance adjustment circuit connected in parallel with the second capacitor between the drain of the third transistor and the first output terminal and including a fourth transistor and a third capacitor connected in series, a gate of the fourth transistor being connected to the bias generation circuit which supplies a gate voltage to the gate of the fourth transistor according to the level of the first input control signal.

8. The high-frequency semiconductor amplifier circuit according to claim 1 , further comprising:
a plurality of input terminals including the first input terminal at which signals having a high frequency can be input, wherein
the bias generation circuit has a plurality of input control signal terminals including the first input control signal terminal, and the bias generation circuit outputs control signals to selectively connect one of the plurality of input terminals to the first output terminal according to signals input to the plurality of input control signal terminals.

9. The high-frequency semiconductor amplifier circuit according to claim 1 , wherein the first, second, and third transistors are n-channel metal-oxide-semiconductor transistors.

10. The high-frequency semiconductor amplifier circuit according to claim 1 , further comprising:
a third capacitor connected between the source of the first transistor and the gate of the first transistor.

Assignees

• Toshiba Kk

Inventors

• Seshita Toshiki
• Kuriyama Yasuhiko

Classifications

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F2203/7239

  the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es) · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F2203/7209

  the gated amplifier being switched from a first band to a second band · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title