Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows

Patent metadata

Field	Value
Publication number	US-10032752-B2
Application number	US-201615348238-A
Country	US
Kind code	B2
Filing date	Nov 10, 2016
Priority date	Oct 3, 2011
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

First claim

The invention claimed is:

1. A microelectronic package, comprising:
a microelectronic element having memory storage array function, the microelectronic element having element contacts extending along a front face of the microelectronic element and arranged in one or more columns, the microelectronic element having a rear face opposite the respective front face;
a substrate having first and second opposed surfaces and first and second opposed edges extending between the first and second surfaces, the first surface having substrate contacts at the first surface, the rear surface of the microelectronic element facing the first surface of the substrate, the element contacts of the microelectronic element electrically connected with the substrate contacts through conductive structure extending above the front face of the microelectronic element; and
terminals exposed at the second surface of the substrate and electrically connected with the substrate contacts, the terminals being disposed at positions within a plurality of columns extending along the second surface of the substrate and being configured to connect the microelectronic package to at least one component external to the microelectronic package,
the terminals including first and second duplicate sets of data terminals and third and fourth duplicate sets of data terminals, the columns of the first and second duplicate sets of data terminals each extending in a first direction, and the columns of the third and fourth duplicate sets of data terminals each extending in a second direction transverse to the first direction, wherein signal assignments of the first and second duplicate sets of data terminals are symmetric about an axis of symmetry extending in the first direction,
the terminals further including other terminals disposed between the first and second duplicate sets of data terminals that are configured to carry signals other than the signals carried by the data terminals.

2. The microelectronic package as claimed in claim 1 , wherein the other terminals disposed between the first and second duplicate sets of data terminals are configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element.

3. A microelectronic package, comprising:
first and second microelectronic elements each having memory storage array function, each microelectronic element having element contacts extending along a front face of such microelectronic element and arranged in one or more columns, each microelectronic element having a rear face opposite the respective front face;
a substrate having first and second opposed surfaces and first and second opposed edges extending between the first and second surfaces, the first surface having first substrate contacts and second substrate contacts at the first surface, the rear surface of each microelectronic element facing the first surface of the substrate, the element contacts of the first microelectronic element electrically connected with the first substrate contacts through first conductive structure extending above the front face of the first microelectronic element, the element contacts of the second microelectronic element electrically connected with the second substrate contacts through second conductive structure extending above the front face of the second microelectronic element; and
terminals exposed at the second surface of the substrate and electrically connected with the first and second substrate contacts, the terminals being disposed at positions within a plurality of columns extending along the second surface of the substrate and being configured to connect the microelectronic package to at least one component external to the microelectronic package,
the terminals including first and second duplicate sets of data terminals and third and fourth duplicate sets of data terminals, the columns of the first and second duplicate sets of data terminals each extending in a first direction, and the columns of the third and fourth duplicate sets of data terminals each extending in a second direction transverse to the first direction, wherein signal assignments of the first and second duplicate sets of data terminals are symmetric about an axis of symmetry extending in the first direction,
the terminals further including other terminals disposed between the first and second duplicate sets of data terminals that are configured to carry signals other than the signals carried by the data terminals.

4. The microelectronic package as claimed in claim 3 , wherein the other terminals disposed between the first and second duplicate sets of data terminals are configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the first and second microelectronic elements.

5. The microelectronic package as claimed in claim 4 , wherein the other terminals disposed between the first and second duplicate sets of data terminals are configured to carry all of the address information usable by the circuitry within the microelectronic package to determine the addressable memory location.

6. The microelectronic assembly as claimed in claim 4 , wherein the other terminals disposed between the first and second duplicate sets of data terminals are configured to carry all of the command signals transferred to the microelectronic package, the command signals being write enable, row address strobe, and column address strobe signals.

7. The microelectronic package as claimed in claim 4 , further comprising a buffer chip having a surface facing the first surface of the substrate, the buffer chip being electrically connected with the other terminals, the buffer chip being configured to regenerate at least some of the address information received at the other terminals and to output the regenerated address information to the first and second microelectronic elements.

8. The microelectronic package as claimed in claim 3 , wherein signal assignments of the third set of data terminals have modulo-X symmetry about the axis of symmetry, wherein X is an integer.

9. The microelectronic package as claimed in claim 8 , wherein X is equal to 2 raised to the power of n, n being greater than or equal to 2.

10. The microelectronic package as claimed in claim 8 , wherein X is equal to N times 8, wherein N is a whole number greater than or equal to one.

11. The microelectronic package as claimed in claim 8 , wherein X is greater than two.

12. The microelectronic package as claimed in claim 3 , wherein signal assignments of the third and fourth duplicate sets of data terminals are symmetric about a second axis of symmetry extending in the second direction.

13. The microelectronic package as claimed in claim 3 , wherein the first and second duplicate sets of data terminals separate the third and fourth duplicate sets of data terminals from one another.

14. The microelectronic package as claimed in claim 3 , wherein the axis of symmetry is located within one ball pitch of the terminals of a centerline of the substrate located equidistant between the first and second opposed edges.

15. The microelectronic package as claimed in claim 3 , wherein each of the first and second microelectronic elements embody a greater number of active devices to provide memory storage array function than any other function.

16. The microelect

Assignees

• Invensas Corp

Inventors

• Crisp Richard Dewitt
• Zohni Wael
• Haba Belgacem
• Lambrecht Frank

Classifications

• G11C5/066

  Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C8/18

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title