Semiconductor package with multiple molding routing layers and a method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10032645-B1
Application number	US-201615347695-A
Country	US
Kind code	B1
Filing date	Nov 9, 2016
Priority date	Nov 10, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is fondled from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

First claim

We claim:

1. A semiconductor package comprising:
package terminals;
a base metal plated routing layer including base metal routing circuits that are plated on a copper leadframe;
at least one additional metal plated routing layer, wherein each of the at least one additional metal plated routing layer includes:
a plurality of interconnections coupled with routing circuits associated with a previous routing layer that is directly beneath a current metal plated routing layer;
an intermediary insulation layer formed on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer that has an unnatural surface roughness that is rougher than the natural surface roughness of the intermediary insulation layer; and
additional metal routing circuits adhered on the unnaturally roughened top surface of the intermediary insulation layer;

a die coupled with a topmost metal plated routing layer;
a topmost insulation layer encapsulating the die and the topmost metal routing layer; and
a bottommost insulation layer encapsulating the base metal routing circuits.

2. The semiconductor package of claim 1 , wherein the base metal routing circuits are formed on a first side of the copper leadframe and the package terminals are formed on a second side of the copper leadframe.

3. The semiconductor package of claim 2 , wherein each of the additional metal routing circuits includes a plurality of metal plated layers.

4. The semiconductor package of claim 3 , wherein the routing circuits associated with each routing layer is structured differently from the routing circuits associated with other routing layers.

5. The semiconductor package of claim 4 , wherein the additional metal routing circuits associated with each of the at least one additional metal plated routing layer is structured differently from the additional metal routing circuits associated with other additional metal plated routing layers.

6. The semiconductor package of claim 5 , wherein molding compound of the intermediary insulation layer surrounds the routing circuits associated with the previous routing layer.

7. The semiconductor package of claim 6 , wherein each of the at least one additional metal plated routing layer further includes bus lines extending from the additional metal routing circuits.

8. The semiconductor package of claim 7 , wherein the bus lines are not exposed at sides of the semiconductor package.

9. The semiconductor package of claim 8 , further comprising an internal routing circuit from die terminals on the die to the package terminals, wherein the internal routing circuit is formed by all the routing layers in the semiconductor package.

10. The semiconductor package of claim 9 , wherein exposed surfaces of the package terminals are flush with a bottom surface of the bottommost insulation layer.

11. A semiconductor package comprising:
package terminals;
a base metal plated routing layer including base metal routing circuits that are plated on a copper leadframe;
at least one additional metal plated routing layer, wherein each of the at least one additional metal plated routing layer includes:
a plurality of interconnections coupled with routing circuits associated with a previous routing layer that is directly beneath a current metal plated routing layer;
an intermediary insulation layer formed on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer that has an unnatural surface roughness that is rougher than the natural surface roughness of the intermediary insulation layer;
additional metal routing circuits adhered on the unnaturally roughened top surface of the intermediary insulation layer; and
bus lines extending from the additional metal routing circuits are not exposed at sides of the semiconductor package;

a die coupled with a topmost metal plated routing layer;
a topmost insulation layer encapsulating the die and the topmost metal routing layer; and
a bottommost insulation layer encapsulating the base metal routing circuits.

12. The semiconductor package of claim 11 , wherein each of the additional metal routing circuits includes a plurality of metal plated layers, wherein each two adjacent metal plated layers of the plurality of metal plated layers sandwich a seed layer.

13. The semiconductor package of claim 11 , wherein the unnatural surface roughness is formed by compound fillers in the intermediary insulation layer protruding beyond compound resin in the intermediary insulation layer.

14. The semiconductor package of claim 11 , wherein the entirety of the top surface of the intermediary insulation layer has the unnatural surface roughness.

15. The semiconductor package of claim 11 , wherein each of the at least one metal routing layer further includes a seed layer between the additional metal routing circuits and the unnaturally roughened top surface of the intermediary insulation layer, wherein the seed layer anchors to the unnaturally roughened top surface of the intermediary insulation layer and has the same pattern as the additional metal routing circuits.

16. The semiconductor package of claim 11 , wherein the package terminals are in electrical communication with the base metal routing circuits via the copper leadframe.

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Sirinorakul Saravuth
• Yenrudee Suebphong

Classifications

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/457

  of metallic layers on leadframes · CPC title