Two part programming and erase methods for non-volatile charge trap memory devices

Patent metadata

Field	Value
Publication number	US-10032518-B2
Application number	US-201715581479-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Sep 14, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array, and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other.

First claim

What is claimed is:

1. An erase operation method of a semiconductor memory device, the method comprising:
applying a first erase control voltage to word lines of a memory cell array that includes a plurality of memory cells during a first erase operation of the erase operation;
applying a set erase voltage to a source line of the memory cell array during the first erase operation;
applying a second erase control voltage to the word lines during a second erase operation of the erase operation; and
sequentially applying normal erase voltages to the source line during the second erase operation,
wherein the set erase voltage has a longer application time than a first normal erase voltage of the normal erase voltages, and
wherein all of the normal erase voltages have a same application time as each other.

2. The method according to claim 1 ,
wherein the first erase control voltage has a lower potential level than the second erase control voltage.

3. The method according to claim 1 ,
wherein the set erase voltage has a higher potential level than the first normal erase voltage of the normal erase voltages.

4. The method according to claim 1 , further comprising:
applying a first program allowable voltage to one or more bit lines of a memory cell array that includes a plurality of memory cells;
applying a set program voltage to a word line selected among a plurality of word lines of the memory cell array;
applying a second program allowable voltage to the one or more bit lines; and
sequentially applying normal program voltages to the selected word line.

5. The method according to claim 4 ,
wherein the first program allowable voltage has a lower potential level than the second program allowable voltage.

6. The method according to claim 4 ,
wherein the set program voltage has a higher potential level than a first normal program voltage of the normal program voltages or a longer application time than the first normal program voltage.

Assignees

• Sk Hynix Inc

Inventors

• Lee Yeonghun

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title