Display panel

Patent metadata

Field	Value
Publication number	US-9672782-B2
Application number	US-94993110-A
Country	US
Kind code	B2
Filing date	Nov 19, 2010
Priority date	Nov 26, 2009
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.

First claim

What is claimed is:

1. A display panel comprising:
a display area including a gate line;
a gate driver connected to one end of the gate line, the gate driver including a plurality of stages and being integrated on a substrate, wherein the plurality of stages receive a clock signal, a first low voltage and a second low voltage, at least one transmission signal from a previous stage, and at least one transmission signal from one of a next stage to output a gate voltage including the first low voltage as a gate-off voltage,
the plurality of stages comprises:
a first transistor including a control terminal that receives the at least one transmission signal from the next stage and an input terminal connected to a first node; and
a second transistor including a control terminal and an input terminal which are connected to an output terminal of the first transistor, and an output terminal which is connected to the second low voltage which is not included in the gate voltage.

2. The display panel of claim 1 , wherein a low voltage of the first or second transmission signal is low is the second low voltage.

3. The display panel of claim 1 , wherein:
the display area further includes a data line,
the display panel further includes a data driver that supplies a data voltage which is applied to the data line,
wherein the data driver is disposed at an upper side or a lower side of the display panel.

4. The display panel of claim 3 , wherein the plurality of stages include an input section, a pull-up driver, a pull-down driver, an output section, and a transmission signal generator.

5. The display panel of claim 4 , wherein the input section, the pull-down driver, the output section, and the transmission signal generator are connected to a first node.

6. The display panel of claim 5 , wherein the input section is connected between a first input terminal that receives the at least one transmission signal from the previous stage and the first node.

7. The display panel of claim 5 , wherein the output section is connected between a gate voltage output terminal that outputs the gate voltage, a clock input terminal input with the clock signal, and the first node, such that the gate voltage is output according to the voltage of the first node.

8. The display panel of claim 5 , wherein the transmission signal generator is connected between a transmission signal output terminal that outputs the transmission signal, the clock input terminal, and the first node, such that the transmission signal is output according to the voltage of the first node.

9. The display panel of claim 5 , wherein the pull-up driver and the pull-down driver are connected to a second node.

10. The display panel of claim 9 , wherein the pull-down driver is connected to a terminal that inputs the at least one transmission signal from the next stage, each terminal that inputs the first low voltage and the second low voltage, respectively, the transmission signal output terminal, and the gate voltage output terminal, and is also connected to the first node and the second node.

11. The display panel of claim 9 , wherein the pull-down driver includes an element that pulls down the first node, an element that pulls down the second node, an element that pulls down the transmission signal output terminal, and an element that pulls down the gate voltage output terminal.

12. The display panel of claim 11 , wherein the element that pulls down the first node decreases the voltage of the first node to the second low voltage according to one of the at least one transmission signal from the next stage or the voltage of the second node.

13. The display panel of claim 11 , wherein the element that pulls down the second node decreases the voltage of the second node to the second low voltage according to the at least one transmission signal from the previous stage or the transmission signal of a current stage.

14. The display panel of claim 11 , wherein the element that pulls down the second node decreases the voltage of the second node to the second low voltage according to at least one transmission signal from the previous stage, and decreases the voltage of the second node to the first low voltage according to the transmission signal of a current stage.

15. The display panel of claim 11 , wherein the element that pulls down the transmission signal output terminal decreases the voltage of the transmission signal output terminal to the second low voltage according to the voltage of the second node.

16. The display panel of claim 11 , wherein the element that pulls down the transmission signal output terminal decreases the voltage of the transmission signal output terminal to the second low voltage according to one of the at least one transmission signal from the next stage.

17. The display panel of claim 11 , wherein the element that pulls down the gate voltage output terminal decreases the voltage of the gate voltage output terminal to the first low voltage according to the voltage of the second node or one of at least two transmission signals from the next stage.

18. The display panel of claim 9 , wherein the pull-up driver is connected to the clock input terminal, the pull-down driver, and the second node.

19. The display panel of claim 1 , wherein:
the at least one transmission signal from the previous stage is the transmission signal of the neighboring previous stage, or
the at least one transmission signal from the next stage is the transmission signals of two next stages that continuously neighbor each other.

20. The display panel of claim 1 , wherein at least one transmission signal applied to a first stage of the plurality of stages is a scanning start signal.

21. The display panel of claim 1 , wherein the plurality of stages comprise:
a third transistor outputting the transmission signal including the second low voltage as a low voltage, and
a fourth transistor receiving the transmission signal from the third transistor of a current stage, and decreases a voltage of a second node to the first low voltage.

22. The display panel of claim 21 , wherein the plurality of stages further comprise:
a fifth transistor receiving the transmission signal from the third transistor of the current stage, and
a sixth transistor and a seventh transistor connected to an input terminal of the fifth transistor,
wherein an output terminal of the fifth transistor is connected to the first low voltage,
wherein a control terminal and an input terminal of the sixth transistor is connected and an output terminal of the sixth transistor is connected to the input terminal of the fifth transistor, and
wherein a control terminal of the seventh transistor is connected to the input terminal of the fifth transistor, an input terminal of the seventh transistor is connected to the control terminal and the input terminal of the sixth transistor, and an output terminal of the seventh transistor is connected to the second node.

23. The display panel of claim 22 , wherein the control terminal and the input terminal of the sixth transistor receive the clock signal.

24. The display panel of claim 22 , wherein the plurality of stages further comprise an eighth transistor that decreases the voltage of the first node to the second low voltage according to a voltage of the second node.

25. The display panel of claim 24 , wherein the plurality of stages further comprise a ninth transistor that decreases th

Assignees

• Lee Jae-Hoon
• Moon Seung-Hwan
• Lee Yong-Soon
• Kim Young-Su
• Lee Chang-Ho
• Lee Whee-Won
• Song Jun-Yong
• Bae Yu-Han
• Samsung Display Co Ltd

Inventors

• Lee Jae-Hoon
• Moon Seung-Hwan
• Lee Yong-Soon
• Kim Young-Su
• Lee Chang-Ho
• Lee Whee-Won
• Song Jun-Yong
• Bae Yu-Han

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title