Techniques for maintaining atomicity and ordering for pixel shader operations

Patent metadata

Field	Value
Publication number	US-10032245-B2
Application number	US-201514924628-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Oct 27, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

First claim

What is claimed is:

1. A graphics processing pipeline, comprising:
a tile coalescer that:
receives a first coverage sample and a second coverage sample in an application programming interface order,
generates a first dataset that includes the first coverage sample, and
generates a second dataset that includes the second coverage sample;

a thread management unit that is coupled to the tile coalescer and:
configures a first thread group to perform a first read-modify-write operation based on the first dataset;
configures a second thread group to perform a second read-modify-write operation based on the second dataset, and
causes the first thread group and the second thread group to execute on one or more multiprocessors in the application programming interface order, wherein the tile coalescer and thread management unit are executed by a parallel processor.

2. The graphics processing pipeline of claim 1 , wherein the tile coalescer generates the first dataset and the second data set by:
identifying a conflict between the first coverage sample and the second coverage sample;
including the first coverage sample in the first dataset; and
including the second coverage sample in the second dataset.

3. The graphics processing pipeline of claim 2 , wherein the tile coalescer identifies the conflict between the first coverage sample and the second coverage sample by determining that the first coverage sample and the second coverage sample both reside at a first X-Y position.

4. The graphics processing pipeline of claim 1 , wherein the thread management unit assigns a first value to the first thread group when configuring the first thread group to perform the first read-modify-write operation, and wherein the thread management unit assigns a second value to the second thread group when configuring the second thread group to perform the second read-modify-write operation.

5. The graphics processing pipeline of claim 4 , wherein a first thread in the first thread group:
acquires a first number from the thread management unit;
determines that the first value is equal to the first number;
in response, initiates the first read-modify-write operation; and
causes the thread management unit to update the first number to reflect a second number, wherein the first thread is executed by the parallel processor.

6. The graphics processing pipeline claim 5 , wherein a second thread in the second thread group:
acquires a second number from the thread management unit;
determines that the second value is equal to the second number;
in response, initiates the second read-modify-write operation; and
causes the thread management unit to update the second number to reflect a third number, wherein the second thread is executed by the parallel processor.

7. The graphics processing pipeline of claim 4 , wherein the thread management unit includes:
a ticket ordering register that stores at least one of the first value and the second value; and
a ticket dispenser register that stores at least one of the first number and the second number.

8. The graphics processing pipeline of claim 1 , wherein each of the first read-modify-write operation and the second read-modify-write operation comprises a programmable blending operation.

9. The graphics processing pipeline claim 1 , wherein the first dataset comprises a first tile associated with a first screen space region, and the second dataset comprises a second tile associated with the first screen space region, wherein the first dataset includes a first set of coverage samples for a first set of locations within the first screen space region, and the second dataset includes a second set of coverage samples for the first set of locations in the first screen space region.

10. The graphics processing pipeline claim 1 , wherein each of the one or more multiprocessors includes at least one load-store unit and at least one execution unit that are configured to perform read-modify-write operations with pixel data stored in a memory unit.

11. The graphics processing pipeline claim 1 , wherein the tile coalescer further transmits the first dataset and the second data set to the thread management unit in the application programming interface order.

12. A computer-implemented method for processing tiles of coverage samples, the method comprising:
receiving a first coverage sample and a second coverage sample in an application programming interface order;
generating a first dataset that includes the first coverage sample;
generating a second dataset that includes the second coverage sample;
configuring a first thread group to perform a first read-modify-write operation based on the first dataset;
configuring a second thread group to perform a second read-modify-write operation based on the second dataset; and
causing the first thread group and the second thread group to execute on one more multiprocessors in the application programming interface order.

13. The computer-implemented method of claim 12 , further comprising generating the first dataset and the second data set by:
identifying a conflict between the first coverage sample and the second coverage sample;
including the first coverage sample in the first dataset; and
including the second coverage sample in the second dataset.

14. The computer-implemented method of claim 13 , further comprising identifying the conflict between the first coverage sample and the second coverage sample by determining that the first coverage sample and the second coverage sample both reside at a first X-Y position.

15. The computer-implemented method of claim 12 , further comprising assigning a first value to the first thread group when configuring the first thread group to perform the first read-modify-write operation, and assigning the first value to the second thread group when configuring the second thread group to perform the second read-modify-write operation.

16. The computer-implemented method of claim 15 , further comprising:
configuring a first thread in the first thread group to:
acquire a first number from a thread management unit,
determine that the first value is equal to the first number,
in response, initiate the first read-modify-write operation, and
cause the thread management unit to update the first number to reflect a second number; and

configuring a second thread in the second thread group to:
acquire the first number from a thread management unit,
determine that the first value is equal to the first number, and
in response, initiate the second read-modify-write operation, wherein the first thread and the second thread are executed by a parallel processor.

17. The computer-implemented method of claim 12 , wherein the thread management unit is associated with a portion of a screen space that includes the first tile and the second tile.

18. The computer-implemented method of claim 13 , further comprising configuring the thread management unit to cause a plurality of tiles included within the portion of the screen space to be processed according to an application programming interface order associated with a plurality of coverage samples associated with the portion of the screen space.

19. A non-transitory computer-readable medium storing program instructions that, when executed by a processor, cause the processor to process tiles of coverage samples, by performing the steps of:
receiving a first coverage sample and a second coverage sample in an application programming interface order;
generating a first dataset that includ

Assignees

• Nvidia Corp

Inventors

• Hakura Ziyad
• Lum Eric
• Kirkland Dale
• Choquette Jack
• Brown Patrick R
• Uralsky Yury Y
• Bolz Jeffrey

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T11/40

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

• G06T1/60

  Memory management · CPC title