DIMM SSD addressing performance techniques

Patent metadata

Field	Value
Publication number	US-10031674-B2
Application number	US-201615060596-A
Country	US
Kind code	B2
Filing date	Mar 3, 2016
Priority date	Oct 7, 2015
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM) (105). The NVDIMM (105) may be installed in a Dual In-Line Memory Module (DIMM) docket (125). The NVDIMM (105) may include a non-volatile memory (130). A device driver (160) may intercept a request for a memory address (605) destined for a host memory controller (115), replace the memory address (605) with a pre-mapped memory address (610) or an alias (705, 710) of the pre-mapped memory address (610), and send the pre-mapped memory address (610) to the host memory controller (115), so that the host memory controller (115) generates a target memory address (615) to NVDIMM (105).

First claim

What is claimed is:

1. A device, comprising:
a Non-Volatile Dual In-Line Memory Module (NVDIMM) installed in a Dual In-Line Memory Module (DIMM) socket, the NVDIMM including a memory and an exposed memory, the exposed memory including a first size of the exposed memory and a base address of the exposed memory; and
a device driver operating on a host processor, the device driver operative to intercept a memory address destined for a host memory controller and replace the memory address with a pre-mapped memory address in a request sent to the host memory controller, the pre-mapped memory address different from the memory address,
wherein the exposed memory includes a directly addressable memory.

2. A device according to claim 1 , wherein the NVDIMM includes an NVDIMM Solid State Device (SSD).

3. A device according to claim 1 , wherein the pre-mapped memory address is designed such that the host memory controller transmits a target memory address to the NVDIMM responsive to the pre-mapped memory address, the target memory address including a physical location of a value stored at the memory address.

4. A device according to claim 3 , wherein the device driver is operative to generate the pre-mapped memory address from the memory address responsive to the first size of the exposed memory in the NVDIMM, the base address of the exposed memory in the NVDIMM, a second size of a logical segment of the exposed memory in the NVDIMM, and a memory controller operating mode of the host memory controller.

5. A device according to claim 3 , wherein the pre-mapped memory address is an alias of a second pre-mapped memory address,
wherein the pre-mapped memory address is different from the second pre-mapped memory address and the host memory controller maps both the pre-mapped memory address and the second pre-mapped memory address to the target memory address.

6. A device according to claim 5 , wherein the pre-mapped memory address includes at least one changed bit relative to the second pre-mapped memory address, the at least one changed bit not impacting the target memory address transmitted from the host memory controller to the NVDIMM.

7. A method, comprising:
receiving a request to access a memory address of a Non-Volatile Dual In-Line Memory Module (NVDIMM), the NVDIMM including a memory and an exposed memory, the exposed memory including a first size of the exposed memory and a base address of the exposed memory;
pre-mapping the memory address to an intermediate address, the intermediate address different from the memory address; and
sending the intermediate address to a host memory controller,
wherein the host memory controller sends a target memory address to the NVDIMM, the target memory address representing a physical location of a value stored at the memory address.

8. A method according to claim 7 , wherein receiving a request to access a memory address includes receiving the request to access the memory address of an NVDIMM Solid State Device (SSD).

9. A method according to claim 7 , wherein pre-mapping the memory address to an intermediate address includes pre-mapping the memory address to the intermediate address responsive to the first size of the exposed memory in the NVDIMM, the base address of the exposed memory in the NVDIMM, a second size of a logical segment of the exposed memory in the NVDIMM, and a memory controller operating mode of the host memory controller.

10. A method according to claim 7 , wherein pre-mapping the memory address to an intermediate address includes pre-mapping the memory address to an alias of a second intermediate address,
wherein the intermediate address is different from the second intermediate address and the host memory controller maps both the intermediate address and the second intermediate address to the target memory address.

11. A method according to claim 10 , wherein pre-mapping the memory address to an intermediate address includes changing at least one bit in the intermediate address relative to the second intermediate address, the at least one changed bit not impacting the target memory address transmitted from the host memory controller to the NVDIMM.

12. A method according to claim 7 , further comprising exposing the exposed memory to the host memory controller.

13. A method according to claim 12 , wherein exposing the exposed memory to the host memory controller includes:
identifying a contiguous block of memory having the first size;
dividing the contiguous block of memory into logical segments, each logical segment having a second size; and
exposing the logical segments to the host memory controller.

14. A method according to claim 7 , wherein the target memory address is responsive to the intermediate address and includes the physical location of the value stored at the memory address.

15. A method according to claim 7 , wherein the exposed memory includes a directly addressable memory.

16. An article, comprising a non-transitory storage medium, the tangible storage medium having stored thereon instructions that, when executed by a machine, result in:
receiving a request to access a memory address of a Non-Volatile Dual In-Line Memory Module (NVDIMM), the NVDIMM including a memory and an exposed memory, the exposed memory including a first size of the exposed memory and a base address of the exposed memory;
pre-mapping the memory address to an intermediate address, the intermediate address different from the memory address; and
sending the intermediate address to a host memory controller,
wherein the host memory controller sends a target memory address to the NVDIMM, the target memory address responsive to the intermediate address and including a physical location of a value stored at the memory address, and
wherein the exposed memory includes a directly addressable memory.

17. An article according to claim 16 , wherein pre-mapping the memory address to an intermediate address includes pre-mapping the memory address to the intermediate address responsive to the first size of the exposed memory in the NVDIMM, the base address of the exposed memory in the NVDIMM, a second size of a logical segment of the exposed memory in the NVDIMM, and a memory controller operating mode of the host memory controller.

18. An article according to claim 16 , wherein pre-mapping the memory address to an intermediate address includes pre-mapping the memory address to an alias of a second intermediate address,
wherein the intermediate address is different from the second intermediate address and the host memory controller maps both the intermediate address and the second intermediate address to the target memory address.

19. An article according to claim 16 , wherein pre-mapping the memory address to an intermediate address includes changing at least one bit in the intermediate address relative to the second intermediate address, the at least one changed bit not impacting the target memory address transmitted from the host memory controller to the NVDIMM.

Assignees

• Hanson Craig
• Swarbrick Ian
• Bekerman Michael
• CHANG Chihjen
• Samsung Electronics Co Ltd

Inventors

• Hanson Craig
• Swarbrick Ian
• Bekerman Michael
• CHANG Chihjen

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F12/0653 Primary

  with centralised address assignment · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title