Communication apparatus and communication method for inverse discrete-fourier-transforming a frequency domain signal into a time domain symbol sequence
US-9516648-B2 · Dec 6, 2016 · US
US10028281B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10028281-B2 |
| Application number | US-201715678948-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 16, 2017 |
| Priority date | Sep 22, 2008 |
| Publication date | Jul 17, 2018 |
| Grant date | Jul 17, 2018 |
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A communication apparatus includes a receiver, a combiner, and a transformer. The receiver receives signals mapped on plural frequency bands. A size of at least one of the frequency bands is a multiple of a product of two or more powers of prime numbers, which are integer numbers greater than 1 and are different from each other. An exponent for at least one of the prime numbers is an integer greater than 1. The combiner combines the received signals into a combined signal. The transformer transforms the combined signal in a frequency domain into a symbol sequence in a time domain with an inverse discrete Fourier transform (IDFT) having a size that is a product of powers of plural values. The values are integer numbers greater than 1 and are different from each other. An exponent for at least one of the values is an integer greater than 1.
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The invention claimed is: 1. An integrated circuit comprising: at least one input which inputs data; and circuitry which is coupled to the at least one input and which controls; reception of signals mapped on a plurality of frequency bands in a frequency domain, each frequency band including a plurality of subcarriers, each frequency band being located at a position separate from position(s) of other(s) of the plurality of frequency bands, and a size of at least one of the plurality of frequency bands being a multiple of a product of two or more powers of prime numbers, the prime numbers being integer numbers that are greater than 1 and are different from each other, exponents for the prime numbers being a set of non-negative integers; combining of the received signals into a combined signal; and transformation of the combined signal in the frequency domain into a symbol sequence in a time domain with an inverse discrete Fourier transform (IDFT) having a size that is a product of powers of a plurality of values, the plurality of values being integer numbers that are greater than 1 and are different from each other, exponents for the plurality of values being a set of non-negative integers. 2. The integrated circuit according to claim 1 , wherein a number of the plurality of frequency bands is two, and a size of one of the two frequency bands is a multiple of a product of two or more powers of prime numbers. 3. The integrated circuit according to claim 1 , wherein the prime numbers are selected in order from a smaller prime number. 4. The integrated circuit according to claim 1 , wherein a size of all of the plurality of frequency bands is a multiple of a product of two or more powers of prime numbers. 5. The integrated circuit according to claim 1 , wherein a first exponent for a first prime number is equal to or greater than a second exponent for a second prime number that is greater than the first prime number. 6. The integrated circuit according to claim 1 , wherein a size of each of the plurality of frequency bands is one minimum division unit or multiple minimum division units, the minimum division unit being a product of two or more powers of prime numbers, wherein a first exponent for a first prime number is equal to or greater than a second exponent for a second prime number that is greater than the first prime number. 7. The integrated circuit according to claim 6 , wherein a size of all of the plurality of frequency bands is a multiple of the minimum division unit. 8. The integrated circuit according to claim 7 , wherein the circuitry controls transmission of allocation information indicating a frequency position of each of the plurality of frequency bands, the frequency position being indicated in terms of the minimum division unit. 9. The integrated circuit according to claim 1 , wherein the circuitry controls transmission of allocation information including the size of at least one of the plurality of frequency bands.
with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM] · CPC title
Transmultiplexing · CPC title
Systems using multi-frequency codes (H04L27/32 takes precedence) · CPC title
Multiplexer/demultiplexer · CPC title
Discrete Fourier transforms · CPC title
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