Ultrashallow emitter formation using ALD and high temperature short time annealing

Patent metadata

Field	Value
Publication number	US-10026815-B2
Application number	US-201414450857-A
Country	US
Kind code	B2
Filing date	Aug 4, 2014
Priority date	Mar 6, 2009
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·1020 atoms/cm3, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.

First claim

What is claimed is:

1. A bipolar transistor, comprising:
a base layer, said base layer having a first conductivity type;
an isolation layer formed on a top surface of said base layer, said isolation layer having an emitter opening such that no isolation layer material is located above said base layer in an area of said emitter opening;
an emitter diffused region formed in said base layer, said emitter diffused region extending from said top surface of said base layer to a depth between 10 and 40 nanometers in said base layer under said emitter opening, said emitter diffused region having a second conductivity type opposite from said first conductivity type, said emitter diffused region having a peak doping density greater than 1·10 20 atoms/cm 3 ;
a polysilicon emitter layer formed above said base layer in said emitter opening, said polysilicon emitter layer having said second conductivity type; and
an emitter dopant atom layer on the top surface of the substrate distinct from and between the polysilicon emitter layer and the emitter diffused region.

2. The bipolar transistor of claim 1 , in which said depth of said emitter diffused region is less than 20 nanometers.

3. The bipolar transistor of claim 1 , in which said peak doping density of said emitter diffused region is greater than 1·10 21 atoms/cm 3 .

4. The bipolar transistor of claim 1 , in which said emitter diffused region is doped with boron.

5. The bipolar transistor of claim 1 , in which said emitter diffused region is doped with phosphorus.

6. The bipolar transistor of claim 1 , in which said emitter diffused region is doped with arsenic.

7. An integrated circuit, comprising:
a bipolar transistor, said bipolar transistor further including:
a base layer, said base layer having a first conductivity type;
an isolation layer formed on a top surface of said base layer, said isolation layer having an emitter opening such that no isolation layer material is located above said base layer in an area of said emitter opening;
an emitter diffused region formed in said base layer, said emitter diffused region extending from said top surface of said base layer to a depth between 10 and 40 nanometers in said base layer under said emitter opening, said emitter diffused region having a second conductivity type opposite from said first conductivity type, said emitter diffused region having a peak doping density greater than 1·10 20 atoms/cm 3 ;
a polysilicon emitter layer formed above said base layer in said emitter opening, said emitter layer having said second conductivity type; and
an emitter dopant atom layer on the top surface of the substrate distinct from and between the polysilicon emitter layer and the emitter diffused region.

8. The integrated circuit of claim 7 , in which said depth of said emitter diffused region is less than 20 nanometers.

9. The integrated circuit of claim 7 , in which said peak doping density of said emitter diffused region is greater than 1·10 21 atoms/cm 3 .

10. The integrated circuit of claim 7 , in which said emitter diffused region is doped with boron.

11. The integrated circuit of claim 7 , in which said emitter diffused region is doped with phosphorus.

12. The integrated circuit of claim 7 , in which said emitter diffused region is doped with arsenic.

13. A bipolar transistor, comprising:
a base layer in a substrate, said base layer having a first conductivity type;
an isolation layer formed on a top surface of the substrate, said isolation layer having an emitter opening;
an emitter diffused region formed in said base layer, said emitter diffused region extending from said top surface of said substrate under said emitter opening, said emitter diffused region having a second conductivity type opposite from said first conductivity type;
a polysilicon emitter layer formed above said base layer in said emitter opening, said polysilicon emitter layer having said second conductivity type; and
an emitter dopant atom layer on the top surface of the substrate distinct from and between the polysilicon emitter layer and the emitter diffused region.

14. The bipolar transistor of claim 13 , in which a depth of the emitter diffused region is less than 20 nanometers.

15. The bipolar transistor of claim 13 , in which a peak doping density of the emitter diffused region is greater than 1·10 21 atoms/cm 3 .

16. The bipolar transistor of claim 13 , in which the emitter diffused region is doped with boron.

17. The bipolar transistor of claim 13 , in which the emitter diffused region is doped with phosphorus.

18. The bipolar transistor of claim 13 , in which the emitter diffused region is doped with arsenic.

Assignees

• Texas Instruments Inc

Inventors

• Wise Rick L
• Yasuda Hiroshi

Classifications

• H10P70/234 Primary

  the processing being the formation of vias or contact holes · CPC title

• H10P32/1408

  from or through or into an external applied layer, e.g. photoresist or nitride layers · CPC title

• H10P32/171

  being group IV material · CPC title

• H01L21/02063

  Electricity · mapped topic

• H01L29/36 Primary

  Electricity · mapped topic