Semiconductor device including an LDMOS transistor and a RESURF structure

Patent metadata

Field	Value
Publication number	US-10026806-B2
Application number	US-201715458492-A
Country	US
Kind code	B2
Filing date	Mar 14, 2017
Priority date	Jun 24, 2016
Publication date	Jul 17, 2018
Grant date	Jul 17, 2018

Abstract

In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≥100 Ohm·cm, a front surface and a rear surface, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a bulk resistivity ρ≥100 Ohm·cm, a front surface and a rear surface;
an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate; and
a RESURF (REduced SURface Field structure) structure comprising a doped buried layer arranged in the semiconductor substrate,
wherein a source region of the LDMOS transistor comprises a first well and a second well having the same conductivity type,
wherein the first well is more highly doped than the second well,
wherein the first well extends to a source side of a gate of the LDMOS transistor and outside of the lateral extent of a body contact region of the LDMOS transistor,
wherein the second well extends further into the substrate than the first well by a distance less than that of a channel region of the LDMOS transistor and is positioned entirely within the body contact region.

2. The semiconductor device of claim 1 , wherein the doped buried layer is spaced at a distance from the front surface and the rear surface, and coupled with at least one of the channel region and the body contact region of the LDMOS transistor, and the RESURF structure further comprises:
a lightly doped region extending from the gate towards a drain region of the LDMOS transistor; and
at least one field plate.

3. The semiconductor device of claim 1 , wherein the RESURF structure is dimensioned such that an electric field at the front surface in a region between the gate and a drain region of the LDMOS transistor is less than 0.5 MV/cm.

4. The semiconductor device of claim 1 , wherein the doped buried layer extends continuously throughout a lateral area of the semiconductor substrate.

5. The semiconductor device of claim 1 , wherein the doped buried layer extends continuously under the source region, the gate and a drain region of the LDMOS transistor.

6. The semiconductor device of claim 1 , further comprising a first dielectric layer on the front surface of the substrate having an opening above a drain region of the LDMOS transistor in which a drain metal contact is formed and an opening over the source region of the LDMOS transistor in which a source metal contact is formed.

7. The semiconductor device of claim 6 , wherein the first dielectric layer covers the gate of the LDMOS transistor and extends between a source-sided gate edge and the source metal contact and between a drain-sided gate edge and the drain metal contact.

8. The semiconductor device of claim 7 , wherein a field plate is positioned on the first dielectric layer above the gate and extends on the first dielectric layer in the direction of the drain metal contact.

9. The semiconductor device of claim 8 , further comprising a second dielectric layer that extends over the source metal contact, over a portion of the first dielectric layer positioned between the source metal contact and the field plate, over the gate, over the field plate, over a portion of the first dielectric layer extending between the field plate and the drain metal contact, and over the drain metal contact.

10. The semiconductor device of claim 9 , further comprising a gate shield arranged on the second dielectric layer above the gate and extending in the direction of the source region.

11. The semiconductor device of claim 10 , wherein the gate shield is conformally deposited on the second dielectric layer and partially overlaps a gate-sided end of the field plate.

12. The semiconductor device of claim 1 , further comprising a conductive via extending from the front surface to the rear surface of the substrate, wherein the conductive via includes a first conductive portion adjacent the rear surface which fills the via and a second conductive portion arranged on the first portion which lines side walls of the via and surrounds a gap, wherein the gap is sealed at the top to form a void within the upper portion of the conductive via.

13. The semiconductor device of claim 12 , wherein the second conductor portion extends over the front surface of the substrate and is arranged directly on and electrically coupled with a conductive layer coupled to a source metal contact at a position adjacent the source region of the LDMOS transistor.

14. A high frequency amplifying circuit comprising the semiconductor device of claim 1 .

15. The high frequency amplifying circuit of claim 14 , wherein the high frequency amplifying circuit comprises an RF power amplifying circuit configured for use in cellular communications operating at frequencies in the range of 700 MHz to 3.6 GHz.

16. The high frequency amplifying circuit of claim 14 , wherein the high frequency amplifying circuit comprises an RF power amplifying circuit configured for use in power conversion in cellular communication networks.

17. The high frequency amplifying circuit of claim 14 , wherein the high frequency amplifying circuit comprises an RF power amplifying circuit configured for use in Doherty configuration amplifying circuits.

18. A semiconductor device, comprising:
a semiconductor substrate having a bulk resistivity ρ≥100 Ohm·cm, a front surface and a rear surface;
an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate;
a RESURF (REduced SURface Field structure) structure comprising a doped buried layer arranged in the semiconductor substrate;
a first dielectric layer on the front surface of the substrate having an opening above a drain region of the LDMOS transistor in which a drain metal contact is formed and an opening over a source region of the LDMOS transistor in which a source metal contact is formed, the first dielectric layer covering a gate of the LDMOS transistor and extending between a source-sided gate edge and the source metal contact and between a drain-sided gate edge and the drain metal contact;
a field plate positioned on the first dielectric layer above the gate and that extends on the first dielectric layer in the direction of the drain metal contact; and
a second dielectric layer that extends over the source metal contact, over a portion of the first dielectric layer positioned between the source metal contact and the field plate, over the gate, over the field plate, over a portion of the first dielectric layer extending between the field plate and the drain metal contact, and over the drain metal contact.

19. The semiconductor device of claim 18 , further comprising a gate shield arranged on the second dielectric layer above the gate and extending in the direction of the source region.

20. The semiconductor device of claim 19 , wherein the gate shield is conformally deposited on the second dielectric layer and partially overlaps a gate-sided end of the field plate.

21. A high frequency amplifying circuit comprising the semiconductor device of claim 18 .

22. The high frequency amplifying circuit of claim 21 , wherein the high frequency amplifying circuit comprises an RF power amplifying circuit configured for use in cellular communications operating at frequencies in the range of 700 MHz to 3.6 GHz.

23. The high frequency amplifying circuit of claim 21 , wherein the high frequency amplifying circuit comprises an RF power amplifying circuit configured for use in power conversion in cellular communication networks.

24. The high frequency amplifying circuit of claim 21 , wherein the high frequency amplifying circuit comprises an RF power amplif

Assignees

• Infineon Technologies Ag

Inventors

• Birner Albert
• Brech Helmut
• Zigldrum Matthias
• Braun Michaela
• Eckl Christian

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title